| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | cz_dpm.c | 521 u32 sclk, vclk, dclk, ecclk, tmp; in cz_dpm_debugfs_print_current_performance_level() local
555 ecclk = vce_table->entries[vce_index].ecclk; in cz_dpm_debugfs_print_current_performance_level()
556 seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk); in cz_dpm_debugfs_print_current_performance_level()
785 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; in cz_dpm_upload_pptable_to_smu()
873 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk; in cz_init_vce_limit()
874 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk; in cz_init_vce_limit()
878 clock = table->entries[level].ecclk; in cz_init_vce_limit()
882 clock = table->entries[table->count - 1].ecclk; in cz_init_vce_limit()
1065 if (clock <= table->entries[i].ecclk) in cz_get_eclk_level()
1071 if (clock >= table->entries[i].ecclk) in cz_get_eclk_level()
[all …]
|
| D | amdgpu.h | 1377 u32 ecclk; member
1472 u32 ecclk; member
1564 u32 ecclk; member
1845 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
|
| D | amdgpu_dpm.c | 547 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
562 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
|
| D | cik.c | 1525 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in cik_set_vce_clocks() argument
1533 ecclk, false, ÷rs); in cik_set_vce_clocks()
|
| D | kv_dpm.c | 2249 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2252 new_rps->ecclk = 0; in kv_apply_state_adjust_rules()
2316 new_rps->evclk || new_rps->ecclk; in kv_apply_state_adjust_rules()
|
| D | vi.c | 1014 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
|
| D | ci_dpm.c | 915 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
918 rps->ecclk = 0; in ci_apply_state_adjust_rules()
|
| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | trinity_dpm.c | 994 (old_rps->ecclk != new_rps->ecclk)) { in trinity_set_vce_clock()
996 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
1000 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1504 u32 evclk, u32 ecclk, u16 *voltage) in trinity_get_vce_clock_voltage() argument
1511 if (((evclk == 0) && (ecclk == 0)) || in trinity_get_vce_clock_voltage()
1519 (ecclk <= table->entries[i].ecclk)) { in trinity_get_vce_clock_voltage()
1555 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in trinity_apply_state_adjust_rules()
1558 new_rps->ecclk = 0; in trinity_apply_state_adjust_rules()
1575 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
|
| D | radeon_asic.h | 697 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
749 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
787 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
|
| D | si_dpm.c | 2957 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
2964 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2972 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
3021 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3022 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3026 rps->ecclk = 0; in si_apply_state_adjust_rules()
5946 (old_rps->ecclk != new_rps->ecclk)) { in si_set_vce_clock()
5948 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5952 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
|
| D | kv_dpm.c | 2155 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2158 new_rps->ecclk = 0; in kv_apply_state_adjust_rules()
2222 new_rps->evclk || new_rps->ecclk; in kv_apply_state_adjust_rules()
|
| D | radeon.h | 1356 u32 ecclk; member
1449 u32 ecclk; member
1540 u32 ecclk; member
1967 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
|
| D | r600_dpm.c | 1106 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in r600_parse_extended_power_table()
1121 rdev->pm.dpm.vce_states[i].ecclk = in r600_parse_extended_power_table()
|
| D | ni.c | 2632 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2638 ecclk, false, ÷rs); in tn_set_vce_clocks()
|
| D | si.c | 7807 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in si_set_vce_clocks() argument
7821 if (!evclk || !ecclk) { in si_set_vce_clocks()
7828 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000, in si_set_vce_clocks()
|
| D | ci_dpm.c | 798 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
801 rps->ecclk = 0; in ci_apply_state_adjust_rules()
|
| D | cik.c | 9750 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in cik_set_vce_clocks() argument
9757 ecclk, false, ÷rs); in cik_set_vce_clocks()
|