Searched refs:dpll_md (Results 1 - 9 of 9) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_crt.c | 93 u32 adpa, dpll_md; cdv_intel_crt_mode_set() local
108 dpll_md = REG_READ(dpll_md_reg); cdv_intel_crt_mode_set()
110 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); cdv_intel_crt_mode_set()
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| H A D | cdv_device.c | 532 .dpll_md = DPLL_A_MD,
557 .dpll_md = DPLL_B_MD,
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| H A D | psb_drv.h | 284 u32 dpll_md; member in struct:psb_offset
318 u32 dpll_md; member in struct:psb_pipe
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| H A D | cdv_intel_display.c | 794 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); cdv_intel_crtc_mode_set()
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| H A D | intel_dsi.c | 703 * set dpll_md = 0 intel_dsi_get_config()
705 pipe_config->dpll_hw_state.dpll_md = 0; intel_dsi_get_config()
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| H A D | intel_display.c | 1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); vlv_enable_pll()
1672 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); chv_enable_pll()
1732 crtc->config->dpll_hw_state.dpll_md); i9xx_enable_pll()
7305 u32 dpll, dpll_md; vlv_compute_dpll() local
7320 dpll_md = (pipe_config->pixel_multiplier - 1) vlv_compute_dpll()
7322 pipe_config->dpll_hw_state.dpll_md = dpll_md; vlv_compute_dpll()
7425 pipe_config->dpll_hw_state.dpll_md = chv_compute_dpll()
7652 u32 dpll_md = (crtc_state->pixel_multiplier - 1) i9xx_compute_dpll() local
7654 crtc_state->dpll_hw_state.dpll_md = dpll_md; i9xx_compute_dpll()
8178 pipe_config->dpll_hw_state.dpll_md = tmp; i9xx_get_pipe_config()
12090 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " intel_dump_pipe_config()
12093 pipe_config->dpll_hw_state.dpll_md, intel_dump_pipe_config()
12610 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); intel_pipe_config_compare()
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| H A D | i915_debugfs.c | 3088 seq_printf(m, " dpll_md: 0x%08x\n", i915_shared_dplls_info()
3089 pll->config.hw_state.dpll_md); i915_shared_dplls_info()
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| H A D | intel_sdvo.c | 1305 /* done in crtc_mode_set as the dpll_md reg must be written early */ intel_sdvo_pre_enable()
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| H A D | i915_drv.h | 367 uint32_t dpll_md; member in struct:intel_dpll_hw_state
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