Searched refs:divq (Results 1 - 5 of 5) sorted by relevance
| /linux-4.4.14/drivers/clk/ |
| H A D | clk-highbank.c | 109 unsigned long divf, divq, vco_freq, reg; clk_pll_recalc_rate() local
116 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; clk_pll_recalc_rate()
119 return vco_freq / (1 << divq); clk_pll_recalc_rate()
125 u32 divq, divf; clk_pll_calc() local
133 for (divq = 1; divq <= 6; divq++) { clk_pll_calc()
134 if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ) clk_pll_calc()
138 vco_freq = rate * (1 << divq); clk_pll_calc()
142 *pdivq = divq; clk_pll_calc()
149 u32 divq, divf; clk_pll_round_rate() local
152 clk_pll_calc(rate, ref_freq, &divq, &divf); clk_pll_round_rate()
154 return (ref_freq * (divf + 1)) / (1 << divq); clk_pll_round_rate()
161 u32 divq, divf; clk_pll_set_rate() local
164 clk_pll_calc(rate, parent_rate, &divq, &divf); clk_pll_set_rate()
174 reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); clk_pll_set_rate()
187 reg |= divq << HB_PLL_DIVQ_SHIFT; clk_pll_set_rate()
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| /linux-4.4.14/drivers/clk/socfpga/ |
| H A D | clk-pll-a10.c | 49 unsigned long divf, divq, reg; clk_pll_recalc_rate() local
55 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; clk_pll_recalc_rate()
57 do_div(vco_freq, (1 + divq)); clk_pll_recalc_rate()
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| H A D | clk-pll.c | 52 unsigned long divf, divq, reg; clk_pll_recalc_rate() local
62 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; clk_pll_recalc_rate()
64 do_div(vco_freq, (1 + divq)); clk_pll_recalc_rate()
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| /linux-4.4.14/drivers/media/pci/solo6x10/ |
| H A D | solo6x10-core.c | 531 u32 divq, divf; solo_pci_probe() local
536 divq = 3; solo_pci_probe()
539 divq = 2; solo_pci_probe()
546 (divq << 12) | solo_pci_probe()
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| /linux-4.4.14/arch/blackfin/lib/ |
| H A D | udivsi3.S | 35 simple divq approach (first setting AQ to 0 - implying unsigned division,
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