Searched refs:div_shift (Results 1 – 6 of 6) sorted by relevance
| /linux-4.4.14/drivers/clk/rockchip/ |
| D | clk.h | 231 u8 div_shift; member
253 .div_shift = ds, \
271 .div_shift = ds, \
289 .div_shift = ds, \
329 .div_shift = ds, \
348 .div_shift = ds, \
364 .div_shift = 16, \
396 .div_shift = s, \
411 .div_shift = s, \
438 .div_shift = shift, \
[all …]
|
| D | clk.c | 44 u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
89 div->shift = div_shift; in rockchip_clk_register_branch()
246 list->div_shift, list->div_width, in rockchip_clk_register_branches()
253 list->div_shift, list->div_width, in rockchip_clk_register_branches()
276 list->div_shift, list->div_width, in rockchip_clk_register_branches()
286 list->div_shift in rockchip_clk_register_branches()
294 list->div_shift, list->div_flags, &clk_lock); in rockchip_clk_register_branches()
|
| /linux-4.4.14/drivers/clk/imx/ |
| D | clk-pllv3.c | 46 u32 div_shift; member
104 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
132 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
133 val |= (div << pll->div_shift); in clk_pllv3_set_rate()
305 pll->div_shift = 1; in imx_clk_pllv3()
|
| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-s3c2410-dclk.c | 171 int div_shift, int cmp_shift) in s3c24xx_dclk_update_cmp() argument
180 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; in s3c24xx_dclk_update_cmp()
|
| /linux-4.4.14/drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 553 u8 div_shift; member
564 .div_shift = _div_shift,\
664 data->div_shift, 8, 1, data->lock); in init_pllp()
|
| /linux-4.4.14/drivers/mfd/ |
| D | db8500-prcmu.c | 523 u32 div_shift; member
530 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
535 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
540 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
1629 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
1968 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); in set_dsiescclk_rate()
|