Searched refs:de_irq_mask (Results 1 - 3 of 3) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_fifo_underrun.c184 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; broadwell_set_fifo_underrun_reporting()
186 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; broadwell_set_fifo_underrun_reporting()
187 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); broadwell_set_fifo_underrun_reporting()
H A Di915_irq.c2676 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; gen8_enable_vblank()
2677 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); gen8_enable_vblank()
2727 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; gen8_disable_vblank()
2728 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); gen8_disable_vblank()
3212 dev_priv->de_irq_mask[PIPE_A], gen8_irq_power_well_post_enable()
3213 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); gen8_irq_power_well_post_enable()
3216 dev_priv->de_irq_mask[PIPE_B], gen8_irq_power_well_post_enable()
3217 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); gen8_irq_power_well_post_enable()
3220 dev_priv->de_irq_mask[PIPE_C], gen8_irq_power_well_post_enable()
3221 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); gen8_irq_power_well_post_enable()
3657 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; gen8_de_irq_postinstall()
3658 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; gen8_de_irq_postinstall()
3659 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; gen8_de_irq_postinstall()
3665 dev_priv->de_irq_mask[pipe], gen8_de_irq_postinstall()
H A Di915_drv.h1765 u32 de_irq_mask[I915_MAX_PIPES]; member in union:drm_i915_private::__anon4247

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