Searched refs:de_irq_mask (Results 1 – 3 of 3) sorted by relevance
184 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; in broadwell_set_fifo_underrun_reporting()186 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; in broadwell_set_fifo_underrun_reporting()187 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in broadwell_set_fifo_underrun_reporting()
2676 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; in gen8_enable_vblank()2677 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_enable_vblank()2727 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; in gen8_disable_vblank()2728 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_disable_vblank()3212 dev_priv->de_irq_mask[PIPE_A], in gen8_irq_power_well_post_enable()3213 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); in gen8_irq_power_well_post_enable()3216 dev_priv->de_irq_mask[PIPE_B], in gen8_irq_power_well_post_enable()3217 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); in gen8_irq_power_well_post_enable()3220 dev_priv->de_irq_mask[PIPE_C], in gen8_irq_power_well_post_enable()3221 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); in gen8_irq_power_well_post_enable()[all …]
1765 u32 de_irq_mask[I915_MAX_PIPES]; member