Searched refs:ddi_pll_sel (Results 1 – 6 of 6) sorted by relevance
638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()639 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); in hsw_fdi_link_train()1063 dpll = pipe_config->ddi_pll_sel; in skl_ddi_clock_get()1111 val = pipe_config->ddi_pll_sel; in hsw_ddi_clock_get()1296 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); in hsw_ddi_pll_select()1297 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { in hsw_ddi_pll_select()1626 crtc_state->ddi_pll_sel = pll->id + 1; in skl_ddi_pll_select()1773 crtc_state->ddi_pll_sel = pll->id; in bxt_ddi_pll_select()2299 uint32_t dpll = crtc->config->ddi_pll_sel; in intel_ddi_pre_enable()2331 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); in intel_ddi_pre_enable()[all …]
183 intel_crtc->config->ddi_pll_sel); in intel_mst_pre_enable_dp()
262 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; in intel_crt_compute_config()
9738 pipe_config->ddi_pll_sel = SKL_DPLL0; in bxt_get_ddi_pll()9742 pipe_config->ddi_pll_sel = SKL_DPLL1; in bxt_get_ddi_pll()9746 pipe_config->ddi_pll_sel = SKL_DPLL2; in bxt_get_ddi_pll()9761 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); in skylake_get_ddi_pll()9763 switch (pipe_config->ddi_pll_sel) { in skylake_get_ddi_pll()9789 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); in haswell_get_ddi_pll()9791 switch (pipe_config->ddi_pll_sel) { in haswell_get_ddi_pll()12065 pipe_config->ddi_pll_sel, in intel_dump_pipe_config()12080 pipe_config->ddi_pll_sel, in intel_dump_pipe_config()12086 pipe_config->ddi_pll_sel, in intel_dump_pipe_config()[all …]
417 uint32_t ddi_pll_sel; member
1119 pipe_config->ddi_pll_sel = SKL_DPLL0; in skl_edp_set_pll_config()1165 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; in hsw_dp_set_ddi_pll_sel()1168 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; in hsw_dp_set_ddi_pll_sel()1171 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; in hsw_dp_set_ddi_pll_sel()