| H A D | armada_crtc.c | 109 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) armada_drm_crtc_update_regs() argument
112 void __iomem *reg = dcrtc->base + regs->offset; armada_drm_crtc_update_regs()
125 static void armada_drm_crtc_update(struct armada_crtc *dcrtc) armada_drm_crtc_update() argument
129 dumb_ctrl = dcrtc->cfg_dumb_ctrl; armada_drm_crtc_update()
131 if (!dpms_blanked(dcrtc->dpms)) armada_drm_crtc_update()
140 if (dpms_blanked(dcrtc->dpms) && armada_drm_crtc_update()
154 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC) armada_drm_crtc_update()
156 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC) armada_drm_crtc_update()
158 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC) armada_drm_crtc_update()
161 if (dcrtc->dumb_ctrl != dumb_ctrl) { armada_drm_crtc_update()
162 dcrtc->dumb_ctrl = dumb_ctrl; armada_drm_crtc_update()
163 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); armada_drm_crtc_update()
194 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, armada_drm_plane_work_run() argument
201 work->fn(dcrtc, plane, work); armada_drm_plane_work_run()
202 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); armada_drm_plane_work_run()
208 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, armada_drm_plane_work_queue() argument
213 ret = drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); armada_drm_plane_work_queue()
221 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); armada_drm_plane_work_queue()
232 struct armada_crtc *dcrtc, struct armada_plane *plane) armada_drm_plane_work_cancel()
237 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); armada_drm_plane_work_cancel()
242 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, armada_drm_crtc_queue_frame_work() argument
245 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); armada_drm_crtc_queue_frame_work()
247 return armada_drm_plane_work_queue(dcrtc, plane, &work->work); armada_drm_crtc_queue_frame_work()
250 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, armada_drm_crtc_complete_frame_work() argument
254 struct drm_device *dev = dcrtc->crtc.dev; armada_drm_crtc_complete_frame_work()
257 spin_lock_irqsave(&dcrtc->irq_lock, flags); armada_drm_crtc_complete_frame_work()
258 armada_drm_crtc_update_regs(dcrtc, fwork->regs); armada_drm_crtc_complete_frame_work()
259 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); armada_drm_crtc_complete_frame_work()
263 drm_send_vblank_event(dev, dcrtc->num, fwork->event); armada_drm_crtc_complete_frame_work()
268 __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb); armada_drm_crtc_complete_frame_work()
272 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, armada_drm_crtc_finish_fb() argument
294 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) armada_drm_crtc_finish_fb()
308 static void armada_drm_vblank_off(struct armada_crtc *dcrtc) armada_drm_vblank_off() argument
310 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); armada_drm_vblank_off()
316 drm_crtc_vblank_off(&dcrtc->crtc); armada_drm_vblank_off()
317 armada_drm_plane_work_run(dcrtc, plane); armada_drm_vblank_off()
333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_dpms() local
335 if (dcrtc->dpms != dpms) { armada_drm_crtc_dpms()
336 dcrtc->dpms = dpms; armada_drm_crtc_dpms()
337 if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms)) armada_drm_crtc_dpms()
338 WARN_ON(clk_prepare_enable(dcrtc->clk)); armada_drm_crtc_dpms()
339 armada_drm_crtc_update(dcrtc); armada_drm_crtc_dpms()
340 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms)) armada_drm_crtc_dpms()
341 clk_disable_unprepare(dcrtc->clk); armada_drm_crtc_dpms()
343 armada_drm_vblank_off(dcrtc); armada_drm_crtc_dpms()
345 drm_crtc_vblank_on(&dcrtc->crtc); armada_drm_crtc_dpms()
358 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_prepare() local
366 plane = dcrtc->plane; armada_drm_crtc_prepare()
374 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_commit() local
376 if (dcrtc->dpms != DRM_MODE_DPMS_ON) { armada_drm_crtc_commit()
377 dcrtc->dpms = DRM_MODE_DPMS_ON; armada_drm_crtc_commit()
378 armada_drm_crtc_update(dcrtc); armada_drm_crtc_commit()
386 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_mode_fixup() local
390 if (!dcrtc->variant->has_spu_adv_reg && armada_drm_crtc_mode_fixup()
395 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); armada_drm_crtc_mode_fixup()
402 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) armada_drm_crtc_irq() argument
404 void __iomem *base = dcrtc->base; armada_drm_crtc_irq()
408 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); armada_drm_crtc_irq()
410 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); armada_drm_crtc_irq()
413 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num); armada_drm_crtc_irq()
415 spin_lock(&dcrtc->irq_lock); armada_drm_crtc_irq()
416 ovl_plane = dcrtc->plane; armada_drm_crtc_irq()
419 armada_drm_plane_work_run(dcrtc, plane); armada_drm_crtc_irq()
422 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { armada_drm_crtc_irq()
426 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); armada_drm_crtc_irq()
427 writel_relaxed(dcrtc->v[i].spu_v_h_total, armada_drm_crtc_irq()
432 val |= dcrtc->v[i].spu_adv_reg; armada_drm_crtc_irq()
436 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) { armada_drm_crtc_irq()
437 writel_relaxed(dcrtc->cursor_hw_pos, armada_drm_crtc_irq()
439 writel_relaxed(dcrtc->cursor_hw_sz, armada_drm_crtc_irq()
444 dcrtc->cursor_update = false; armada_drm_crtc_irq()
445 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); armada_drm_crtc_irq()
448 spin_unlock(&dcrtc->irq_lock); armada_drm_crtc_irq()
451 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); armada_drm_crtc_irq()
452 armada_drm_plane_work_run(dcrtc, plane); armada_drm_crtc_irq()
458 struct armada_crtc *dcrtc = arg; armada_drm_irq() local
459 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); armada_drm_irq()
465 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); armada_drm_irq()
468 v = stat & dcrtc->irq_ena; armada_drm_irq()
471 armada_drm_crtc_irq(dcrtc, stat); armada_drm_irq()
478 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) armada_drm_crtc_disable_irq() argument
480 if (dcrtc->irq_ena & mask) { armada_drm_crtc_disable_irq()
481 dcrtc->irq_ena &= ~mask; armada_drm_crtc_disable_irq()
482 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); armada_drm_crtc_disable_irq()
486 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) armada_drm_crtc_enable_irq() argument
488 if ((dcrtc->irq_ena & mask) != mask) { armada_drm_crtc_enable_irq()
489 dcrtc->irq_ena |= mask; armada_drm_crtc_enable_irq()
490 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); armada_drm_crtc_enable_irq()
491 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) armada_drm_crtc_enable_irq()
492 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); armada_drm_crtc_enable_irq()
496 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) armada_drm_crtc_calculate_csc() argument
498 struct drm_display_mode *adj = &dcrtc->crtc.mode; armada_drm_crtc_calculate_csc()
501 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709) armada_drm_crtc_calculate_csc()
503 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO) armada_drm_crtc_calculate_csc()
516 if (dcrtc->csc_yuv_mode == CSC_AUTO) armada_drm_crtc_calculate_csc()
526 if (dcrtc->csc_rgb_mode == CSC_AUTO) armada_drm_crtc_calculate_csc()
537 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_mode_set() local
548 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb, armada_drm_crtc_mode_set()
568 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), armada_drm_crtc_mode_set()
573 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA; armada_drm_crtc_mode_set()
574 if (val != dcrtc->dumb_ctrl) { armada_drm_crtc_mode_set()
575 dcrtc->dumb_ctrl = val; armada_drm_crtc_mode_set()
576 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); armada_drm_crtc_mode_set()
583 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms)) armada_drm_crtc_mode_set()
584 WARN_ON(clk_prepare_enable(dcrtc->clk)); armada_drm_crtc_mode_set()
587 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); armada_drm_crtc_mode_set()
593 if (interlaced ^ dcrtc->interlaced) { armada_drm_crtc_mode_set()
595 drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); armada_drm_crtc_mode_set()
597 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); armada_drm_crtc_mode_set()
598 dcrtc->interlaced = interlaced; armada_drm_crtc_mode_set()
601 spin_lock_irqsave(&dcrtc->irq_lock, flags); armada_drm_crtc_mode_set()
604 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | armada_drm_crtc_mode_set()
606 dcrtc->v[1].spu_v_porch = tm << 16 | bm; armada_drm_crtc_mode_set()
608 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | armada_drm_crtc_mode_set()
609 dcrtc->variant->spu_adv_reg; armada_drm_crtc_mode_set()
613 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + armada_drm_crtc_mode_set()
615 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; armada_drm_crtc_mode_set()
617 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | armada_drm_crtc_mode_set()
618 dcrtc->variant->spu_adv_reg; armada_drm_crtc_mode_set()
620 dcrtc->v[0] = dcrtc->v[1]; armada_drm_crtc_mode_set()
629 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); armada_drm_crtc_mode_set()
630 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, armada_drm_crtc_mode_set()
633 if (dcrtc->variant->has_spu_adv_reg) { armada_drm_crtc_mode_set()
634 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, armada_drm_crtc_mode_set()
640 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); armada_drm_crtc_mode_set()
641 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); armada_drm_crtc_mode_set()
643 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) armada_drm_crtc_mode_set()
658 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc); armada_drm_crtc_mode_set()
662 armada_drm_crtc_update_regs(dcrtc, regs); armada_drm_crtc_mode_set()
663 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); armada_drm_crtc_mode_set()
665 armada_drm_crtc_update(dcrtc); armada_drm_crtc_mode_set()
668 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); armada_drm_crtc_mode_set()
677 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_mode_set_base() local
682 dcrtc->interlaced); armada_drm_crtc_mode_set_base()
686 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), armada_drm_crtc_mode_set_base()
693 armada_drm_crtc_update_regs(dcrtc, regs); armada_drm_crtc_mode_set_base()
696 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); armada_drm_crtc_mode_set_base()
701 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, armada_drm_crtc_plane_disable() argument
728 spin_lock_irq(&dcrtc->irq_lock); armada_drm_crtc_plane_disable()
729 armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); armada_drm_crtc_plane_disable()
730 spin_unlock_irq(&dcrtc->irq_lock); armada_drm_crtc_plane_disable()
732 armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); armada_drm_crtc_plane_disable()
738 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_disable() local
741 armada_drm_crtc_plane_disable(dcrtc, crtc->primary); armada_drm_crtc_disable()
798 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) armada_drm_crtc_cursor_update() argument
800 uint32_t xoff, xscr, w = dcrtc->cursor_w, s; armada_drm_crtc_cursor_update()
801 uint32_t yoff, yscr, h = dcrtc->cursor_h; armada_drm_crtc_cursor_update()
808 if (dcrtc->cursor_x < 0) { armada_drm_crtc_cursor_update()
809 xoff = -dcrtc->cursor_x; armada_drm_crtc_cursor_update()
812 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { armada_drm_crtc_cursor_update()
814 xscr = dcrtc->cursor_x; armada_drm_crtc_cursor_update()
815 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); armada_drm_crtc_cursor_update()
818 xscr = dcrtc->cursor_x; armada_drm_crtc_cursor_update()
821 if (dcrtc->cursor_y < 0) { armada_drm_crtc_cursor_update()
822 yoff = -dcrtc->cursor_y; armada_drm_crtc_cursor_update()
825 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { armada_drm_crtc_cursor_update()
827 yscr = dcrtc->cursor_y; armada_drm_crtc_cursor_update()
828 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); armada_drm_crtc_cursor_update()
831 yscr = dcrtc->cursor_y; armada_drm_crtc_cursor_update()
835 s = dcrtc->cursor_w; armada_drm_crtc_cursor_update()
836 if (dcrtc->interlaced) { armada_drm_crtc_cursor_update()
842 if (!dcrtc->cursor_obj || !h || !w) { armada_drm_crtc_cursor_update()
843 spin_lock_irq(&dcrtc->irq_lock); armada_drm_crtc_cursor_update()
844 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); armada_drm_crtc_cursor_update()
845 dcrtc->cursor_update = false; armada_drm_crtc_cursor_update()
846 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); armada_drm_crtc_cursor_update()
847 spin_unlock_irq(&dcrtc->irq_lock); armada_drm_crtc_cursor_update()
851 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); armada_drm_crtc_cursor_update()
853 dcrtc->base + LCD_SPU_SRAM_PARA1); armada_drm_crtc_cursor_update()
860 armada_drm_crtc_cursor_tran(dcrtc->base); armada_drm_crtc_cursor_update()
864 if (dcrtc->cursor_hw_sz != (h << 16 | w)) { armada_drm_crtc_cursor_update()
865 spin_lock_irq(&dcrtc->irq_lock); armada_drm_crtc_cursor_update()
866 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); armada_drm_crtc_cursor_update()
867 dcrtc->cursor_update = false; armada_drm_crtc_cursor_update()
868 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); armada_drm_crtc_cursor_update()
869 spin_unlock_irq(&dcrtc->irq_lock); armada_drm_crtc_cursor_update()
873 struct armada_gem_object *obj = dcrtc->cursor_obj; armada_drm_crtc_cursor_update()
878 armada_load_cursor_argb(dcrtc->base, pix, s, w, h); armada_drm_crtc_cursor_update()
882 spin_lock_irq(&dcrtc->irq_lock); armada_drm_crtc_cursor_update()
883 dcrtc->cursor_hw_pos = yscr << 16 | xscr; armada_drm_crtc_cursor_update()
884 dcrtc->cursor_hw_sz = h << 16 | w; armada_drm_crtc_cursor_update()
885 dcrtc->cursor_update = true; armada_drm_crtc_cursor_update()
886 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); armada_drm_crtc_cursor_update()
887 spin_unlock_irq(&dcrtc->irq_lock); armada_drm_crtc_cursor_update()
901 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_cursor_set() local
906 if (!dcrtc->variant->has_spu_adv_reg) armada_drm_crtc_cursor_set()
932 if (dcrtc->cursor_obj) { armada_drm_crtc_cursor_set()
933 dcrtc->cursor_obj->update = NULL; armada_drm_crtc_cursor_set()
934 dcrtc->cursor_obj->update_data = NULL; armada_drm_crtc_cursor_set()
935 drm_gem_object_unreference(&dcrtc->cursor_obj->obj); armada_drm_crtc_cursor_set()
937 dcrtc->cursor_obj = obj; armada_drm_crtc_cursor_set()
938 dcrtc->cursor_w = w; armada_drm_crtc_cursor_set()
939 dcrtc->cursor_h = h; armada_drm_crtc_cursor_set()
940 ret = armada_drm_crtc_cursor_update(dcrtc, true); armada_drm_crtc_cursor_set()
942 obj->update_data = dcrtc; armada_drm_crtc_cursor_set()
953 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_cursor_move() local
957 if (!dcrtc->variant->has_spu_adv_reg) armada_drm_crtc_cursor_move()
961 dcrtc->cursor_x = x; armada_drm_crtc_cursor_move()
962 dcrtc->cursor_y = y; armada_drm_crtc_cursor_move()
963 ret = armada_drm_crtc_cursor_update(dcrtc, false); armada_drm_crtc_cursor_move()
971 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_destroy() local
974 if (dcrtc->cursor_obj) armada_drm_crtc_destroy()
975 drm_gem_object_unreference(&dcrtc->cursor_obj->obj); armada_drm_crtc_destroy()
977 priv->dcrtc[dcrtc->num] = NULL; armada_drm_crtc_destroy()
978 drm_crtc_cleanup(&dcrtc->crtc); armada_drm_crtc_destroy()
980 if (!IS_ERR(dcrtc->clk)) armada_drm_crtc_destroy()
981 clk_disable_unprepare(dcrtc->clk); armada_drm_crtc_destroy()
983 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); armada_drm_crtc_destroy()
985 of_node_put(dcrtc->crtc.port); armada_drm_crtc_destroy()
987 kfree(dcrtc); armada_drm_crtc_destroy()
997 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_page_flip() local
1012 work->old_fb = dcrtc->crtc.primary->fb; armada_drm_crtc_page_flip()
1015 dcrtc->interlaced); armada_drm_crtc_page_flip()
1024 ret = armada_drm_crtc_queue_frame_work(dcrtc, work); armada_drm_crtc_page_flip()
1038 dcrtc->crtc.primary->fb = fb; armada_drm_crtc_page_flip()
1044 if (dpms_blanked(dcrtc->dpms)) armada_drm_crtc_page_flip()
1045 armada_drm_plane_work_run(dcrtc, drm_to_armada_plane(dcrtc->crtc.primary)); armada_drm_crtc_page_flip()
1055 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_set_property() local
1059 dcrtc->csc_yuv_mode = val; armada_drm_crtc_set_property()
1062 dcrtc->csc_rgb_mode = val; armada_drm_crtc_set_property()
1069 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_set_property()
1070 armada_drm_crtc_calculate_csc(dcrtc); armada_drm_crtc_set_property()
1071 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL); armada_drm_crtc_set_property()
1136 struct armada_crtc *dcrtc; armada_drm_crtc_create() local
1149 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); armada_drm_crtc_create()
1150 if (!dcrtc) { armada_drm_crtc_create()
1156 dev_set_drvdata(dev, dcrtc); armada_drm_crtc_create()
1158 dcrtc->variant = variant; armada_drm_crtc_create()
1159 dcrtc->base = base; armada_drm_crtc_create()
1160 dcrtc->num = drm->mode_config.num_crtc; armada_drm_crtc_create()
1161 dcrtc->clk = ERR_PTR(-EINVAL); armada_drm_crtc_create()
1162 dcrtc->csc_yuv_mode = CSC_AUTO; armada_drm_crtc_create()
1163 dcrtc->csc_rgb_mode = CSC_AUTO; armada_drm_crtc_create()
1164 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; armada_drm_crtc_create()
1165 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; armada_drm_crtc_create()
1166 spin_lock_init(&dcrtc->irq_lock); armada_drm_crtc_create()
1167 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; armada_drm_crtc_create()
1170 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); armada_drm_crtc_create()
1171 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); armada_drm_crtc_create()
1172 writel_relaxed(dcrtc->spu_iopad_ctrl, armada_drm_crtc_create()
1173 dcrtc->base + LCD_SPU_IOPAD_CONTROL); armada_drm_crtc_create()
1174 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); armada_drm_crtc_create()
1177 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); armada_drm_crtc_create()
1178 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); armada_drm_crtc_create()
1179 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN); armada_drm_crtc_create()
1180 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); armada_drm_crtc_create()
1181 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); armada_drm_crtc_create()
1184 dcrtc); armada_drm_crtc_create()
1186 kfree(dcrtc); armada_drm_crtc_create()
1190 if (dcrtc->variant->init) { armada_drm_crtc_create()
1191 ret = dcrtc->variant->init(dcrtc, dev); armada_drm_crtc_create()
1193 kfree(dcrtc); armada_drm_crtc_create()
1199 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); armada_drm_crtc_create()
1201 priv->dcrtc[dcrtc->num] = dcrtc; armada_drm_crtc_create()
1203 dcrtc->crtc.port = port; armada_drm_crtc_create()
1225 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL, armada_drm_crtc_create()
1230 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); armada_drm_crtc_create()
1232 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, armada_drm_crtc_create()
1233 dcrtc->csc_yuv_mode); armada_drm_crtc_create()
1234 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop, armada_drm_crtc_create()
1235 dcrtc->csc_rgb_mode); armada_drm_crtc_create()
1237 return armada_overlay_plane_create(drm, 1 << dcrtc->num); armada_drm_crtc_create()
1293 struct armada_crtc *dcrtc = dev_get_drvdata(dev); armada_lcd_unbind() local
1295 armada_drm_crtc_destroy(&dcrtc->crtc); armada_lcd_unbind()
231 armada_drm_plane_work_cancel( struct armada_crtc *dcrtc, struct armada_plane *plane) armada_drm_plane_work_cancel() argument
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