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Searched refs:cpu_transcoder (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_ddi.c1808 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_ddi_set_pipe_settings() local
1830 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); in intel_ddi_set_pipe_settings()
1839 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_ddi_set_vc_payload_alloc() local
1841 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_set_vc_payload_alloc()
1846 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); in intel_ddi_set_vc_payload_alloc()
1857 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_ddi_enable_transcoder_func() local
1888 if (cpu_transcoder == TRANSCODER_EDP) { in intel_ddi_enable_transcoder_func()
1948 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); in intel_ddi_enable_transcoder_func()
1952 enum transcoder cpu_transcoder) in intel_ddi_disable_transcoder_func() argument
1954 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); in intel_ddi_disable_transcoder_func()
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Dintel_psr.c82 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in intel_psr_write_vsc() local
83 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in intel_psr_write_vsc()
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, in intel_psr_write_vsc()
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, in intel_psr_write_vsc()
315 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & in intel_psr_match_conditions()
Dintel_display.c1093 return intel_crtc->config->cpu_transcoder; in intel_pipe_to_cpu_transcoder()
1135 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in intel_wait_for_pipe_off() local
1139 int reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in assert_fdi_tx() local
1227 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1349 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in assert_pipe() local
1358 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { in assert_pipe()
1361 u32 val = I915_READ(PIPECONF(cpu_transcoder)); in assert_pipe()
2021 enum transcoder cpu_transcoder) in lpt_enable_pch_transcoder() argument
2029 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); in lpt_enable_pch_transcoder()
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Dintel_hdmi.c117 enum transcoder cpu_transcoder, in hsw_dip_data_reg() argument
123 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
125 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
127 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
369 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in hsw_write_infoframe() local
370 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in hsw_write_infoframe()
375 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); in hsw_write_infoframe()
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, in hsw_write_infoframe()
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, in hsw_write_infoframe()
404 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); in hsw_infoframe_enabled()
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Dintel_dp_mst.c249 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_dp_mst_enc_get_config() local
254 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_dp_mst_enc_get_config()
Dintel_drv.h367 enum transcoder cpu_transcoder; member
984 enum transcoder cpu_transcoder);
Dintel_panel.c900 enum transcoder cpu_transcoder = in pch_enable_backlight() local
918 if (cpu_transcoder == TRANSCODER_EDP) in pch_enable_backlight()
921 cpu_ctl2 = BLM_PIPE(cpu_transcoder); in pch_enable_backlight()
Di915_debugfs.c3826 if (pipe_config->cpu_transcoder == TRANSCODER_EDP && in hsw_trans_edp_pipe_A_crc_wa()
Dintel_dp.c5581 u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder); in intel_dp_set_drrs_state()