Searched refs:cp_int_cntl (Results 1 – 7 of 7) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v8_0.c | 4789 u32 cp_int_cntl; in gfx_v8_0_set_gfx_eop_interrupt_state() local
4793 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v8_0_set_gfx_eop_interrupt_state()
4794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v8_0_set_gfx_eop_interrupt_state()
4796 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v8_0_set_gfx_eop_interrupt_state()
4799 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v8_0_set_gfx_eop_interrupt_state()
4800 cp_int_cntl = in gfx_v8_0_set_gfx_eop_interrupt_state()
4801 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v8_0_set_gfx_eop_interrupt_state()
4803 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v8_0_set_gfx_eop_interrupt_state()
4859 u32 cp_int_cntl; in gfx_v8_0_set_priv_reg_fault_state() local
4863 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v8_0_set_priv_reg_fault_state()
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| D | gfx_v7_0.c | 5298 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
5302 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
5303 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
5304 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
5307 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
5308 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
5309 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
5363 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
5367 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
5368 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state()
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| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | evergreen.c | 209 int ring, u32 cp_int_cntl);
4602 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4649 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4662 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4663 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4765 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4769 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
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| D | ni.c | 1397 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1402 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
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| D | r600.c | 3717 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3775 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3776 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3827 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
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| D | si.c | 6067 u32 cp_int_cntl; in si_irq_set() local
6087 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6108 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6182 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
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| D | cik.c | 7462 u32 cp_int_cntl; in cik_irq_set() local
7481 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7483 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7500 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7600 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
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