| /linux-4.4.14/arch/arm/kernel/ |
| H A D | Makefile | 67 obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
68 obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
69 obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
70 obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
71 obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o
76 CFLAGS_pj4-cp0.o := -marm
|
| H A D | pj4-cp0.c | 2 * linux/arch/arm/kernel/pj4-cp0.c
|
| H A D | xscale-cp0.c | 2 * linux/arch/arm/kernel/xscale-cp0.c
|
| /linux-4.4.14/security/tomoyo/ |
| H A D | realpath.c | 27 char *cp0; tomoyo_encode2() local
46 cp0 = cp; tomoyo_encode2()
63 return cp0; tomoyo_encode2()
|
| H A D | common.c | 2588 char *cp0 = head->write_buf; tomoyo_write_control() local
2608 memmove(cp, cp0, head->w.avail); tomoyo_write_control()
2609 kfree(cp0); tomoyo_write_control()
2611 cp0 = cp; tomoyo_write_control()
2620 cp0[head->w.avail++] = c; tomoyo_write_control()
2623 cp0[head->w.avail - 1] = '\0'; tomoyo_write_control()
2625 tomoyo_normalize_line(cp0); tomoyo_write_control()
2626 if (!strcmp(cp0, "reset")) { tomoyo_write_control()
2638 if (tomoyo_select_domain(head, cp0)) tomoyo_write_control()
2642 if (!strcmp(cp0, "select transition_only")) { tomoyo_write_control()
2653 switch (tomoyo_parse_policy(head, cp0)) { tomoyo_write_control()
|
| /linux-4.4.14/arch/mips/include/asm/ |
| H A D | stackframe.h | 389 * Set cp0 enable bit as sign that we're running on the kernel stack
402 * Set cp0 enable bit as sign that we're running on the kernel stack
416 * Set cp0 enable bit as sign that we're running on the kernel stack
|
| H A D | processor.h | 250 /* Saved cp0 stuff. */
307 * Saved cp0 stuff \
|
| H A D | asm.h | 399 * Some cp0 registers were extended to 64bit for MIPS III.
|
| H A D | mipsregs.h | 85 * R4640/R4650 cp0 register names. These registers are listed
258 * Bitfields in the R4xx0 cp0 status register
281 * Bitfields in the R[23]000 cp0 status register.
|
| /linux-4.4.14/arch/xtensa/include/asm/ |
| H A D | thread_info.h | 33 xtregs_cp0_t cp0; member in struct:xtregs_coprocessor
|
| H A D | elf.h | 182 xtregs_cp0_t cp0; member in struct:__anon3238
|
| /linux-4.4.14/arch/xtensa/kernel/ |
| H A D | ptrace.c | 140 ret |= __copy_to_user(&xtregs->cp0, &ti->xtregs_cp, ptrace_getxregs()
166 ret |= __copy_from_user(&ti->xtregs_cp, &xtregs->cp0, ptrace_setxregs()
|
| /linux-4.4.14/arch/mips/kernel/ |
| H A D | idle.c | 95 * since coreclock (and the cp0 counter) stops upon executing it. Only an
240 * between using the cp0 timer as clocksource or avoiding check_wait()
|
| H A D | traps.c | 277 * Saved cp0 registers __show_regs()
|
| /linux-4.4.14/arch/mips/mm/ |
| H A D | tlbex.c | 420 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ build_r3000_tlb_refill_handler()
426 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ build_r3000_tlb_refill_handler()
432 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ build_r3000_tlb_refill_handler()
433 uasm_i_tlbwr(&p); /* cp0 delay */ build_r3000_tlb_refill_handler()
1717 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ build_r3000_pte_reload_tlbwi()
1718 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ build_r3000_pte_reload_tlbwi()
1736 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ build_r3000_tlb_reload_write()
1737 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ build_r3000_tlb_reload_write()
1739 uasm_i_tlbwi(p); /* cp0 delay */ build_r3000_tlb_reload_write()
1743 uasm_i_tlbwr(p); /* cp0 delay */ build_r3000_tlb_reload_write()
1755 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ build_r3000_tlbchange_handler_head()
1761 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ build_r3000_tlbchange_handler_head()
|
| /linux-4.4.14/arch/mips/sgi-ip27/ |
| H A D | ip27-nmi.c | 83 * Saved cp0 registers nmi_cpu_eframe_save()
|
| /linux-4.4.14/arch/unicore32/kernel/ |
| H A D | setup.c | 323 "Cache clean\t: cp0 c5 ops\n" c_show()
|
| /linux-4.4.14/drivers/scsi/ |
| H A D | u14-34f.c | 1751 panic("%s: ihdlr, invalid mscp bus address %p, cp0 %p.\n", BN(j), ihdlr()
|
| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| H A D | ni.c | 1737 /* this only test cp0 */ cayman_cp_resume()
|