Searched refs:conf_reg (Results 1 - 16 of 16) sorted by relevance

/linux-4.4.14/drivers/tty/serial/
H A Dmen_z135_uart.c486 u32 conf_reg; men_z135_set_mctrl() local
488 conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG); men_z135_set_mctrl()
490 conf_reg |= MEN_Z135_MCR_RTS; men_z135_set_mctrl()
492 conf_reg &= ~MEN_Z135_MCR_RTS; men_z135_set_mctrl()
495 conf_reg |= MEN_Z135_MCR_DTR; men_z135_set_mctrl()
497 conf_reg &= ~MEN_Z135_MCR_DTR; men_z135_set_mctrl()
500 conf_reg |= MEN_Z135_MCR_OUT1; men_z135_set_mctrl()
502 conf_reg &= ~MEN_Z135_MCR_OUT1; men_z135_set_mctrl()
505 conf_reg |= MEN_Z135_MCR_OUT2; men_z135_set_mctrl()
507 conf_reg &= ~MEN_Z135_MCR_OUT2; men_z135_set_mctrl()
510 conf_reg |= MEN_Z135_MCR_LOOP; men_z135_set_mctrl()
512 conf_reg &= ~MEN_Z135_MCR_LOOP; men_z135_set_mctrl()
514 if (conf_reg != old) men_z135_set_mctrl()
515 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); men_z135_set_mctrl()
618 u32 conf_reg = 0; men_z135_startup() local
624 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); men_z135_startup()
627 conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN; men_z135_startup()
628 conf_reg &= ~(0xff << 16); men_z135_startup()
629 conf_reg |= (txlvl << 16); men_z135_startup()
630 conf_reg |= (rxlvl << 20); men_z135_startup()
632 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); men_z135_startup()
643 u32 conf_reg = 0; men_z135_shutdown() local
645 conf_reg |= MEN_Z135_ALL_IRQS; men_z135_shutdown()
647 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg); men_z135_shutdown()
658 u32 conf_reg; men_z135_set_termios() local
663 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); men_z135_set_termios()
664 lcr = LCR(conf_reg); men_z135_set_termios()
697 conf_reg |= MEN_Z135_IER_MSIEN; men_z135_set_termios()
699 conf_reg |= MEN_Z135_MCR_RCFC; men_z135_set_termios()
703 conf_reg &= ~MEN_Z135_MCR_RCFC; men_z135_set_termios()
709 conf_reg |= lcr << MEN_Z135_LCR_SHIFT; men_z135_set_termios()
710 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); men_z135_set_termios()
/linux-4.4.14/drivers/pinctrl/freescale/
H A Dpinctrl-imx.c390 if (pin_reg->conf_reg == -1) { imx_pinconf_get()
396 *config = readl(ipctl->base + pin_reg->conf_reg); imx_pinconf_get()
413 if (pin_reg->conf_reg == -1) { imx_pinconf_set()
425 reg = readl(ipctl->base + pin_reg->conf_reg); imx_pinconf_set()
428 writel(reg, ipctl->base + pin_reg->conf_reg); imx_pinconf_set()
430 writel(configs[i], ipctl->base + pin_reg->conf_reg); imx_pinconf_set()
433 pin_reg->conf_reg, configs[i]); imx_pinconf_set()
447 if (!pin_reg || pin_reg->conf_reg == -1) { imx_pinconf_dbg_show()
452 config = readl(ipctl->base + pin_reg->conf_reg); imx_pinconf_dbg_show()
547 u32 conf_reg; imx_pinctrl_parse_groups() local
556 conf_reg = mux_reg; imx_pinctrl_parse_groups()
558 conf_reg = be32_to_cpu(*list++); imx_pinctrl_parse_groups()
559 if (!conf_reg) imx_pinctrl_parse_groups()
560 conf_reg = -1; imx_pinctrl_parse_groups()
563 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; imx_pinctrl_parse_groups()
568 pin_reg->conf_reg = conf_reg; imx_pinctrl_parse_groups()
719 info->pin_regs[i].conf_reg = -1; imx_pinctrl_probe()
H A Dpinctrl-imx.h67 * @conf_reg: config register offset
71 s16 conf_reg; member in struct:imx_pin_reg
/linux-4.4.14/drivers/hwmon/
H A Demc2103.c435 u8 conf_reg; set_pwm_enable() local
454 result = read_u8_from_i2c(client, REG_FAN_CONF1, &conf_reg); set_pwm_enable()
461 conf_reg |= 0x80; set_pwm_enable()
463 conf_reg &= ~0x80; set_pwm_enable()
465 i2c_smbus_write_byte_data(client, REG_FAN_CONF1, conf_reg); set_pwm_enable()
/linux-4.4.14/drivers/pinctrl/intel/
H A Dpinctrl-baytrail.c328 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG); byt_gpio_direction_output() local
341 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, byt_gpio_direction_output()
/linux-4.4.14/arch/arm/boot/dts/
H A Dimx25-pinfunc.h17 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx51-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6ul-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx35-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx50-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6q-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx53-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6dl-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6sl-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx7d-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6sx-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>

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