Searched refs:con0 (Results 1 - 3 of 3) sorted by relevance
| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk-pll.c | 401 u32 con0, con1; samsung_pll45xx_set_rate() local
412 con0 = __raw_readl(pll->con_reg); samsung_pll45xx_set_rate()
415 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { samsung_pll45xx_set_rate()
417 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); samsung_pll45xx_set_rate()
418 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; samsung_pll45xx_set_rate()
419 __raw_writel(con0, pll->con_reg); samsung_pll45xx_set_rate()
425 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | samsung_pll45xx_set_rate()
428 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | samsung_pll45xx_set_rate()
451 __raw_writel(con0, pll->con_reg); samsung_pll45xx_set_rate()
552 u32 con0, con1, lock; samsung_pll46xx_set_rate() local
563 con0 = __raw_readl(pll->con_reg); samsung_pll46xx_set_rate()
566 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { samsung_pll46xx_set_rate()
568 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); samsung_pll46xx_set_rate()
569 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; samsung_pll46xx_set_rate()
570 __raw_writel(con0, pll->con_reg); samsung_pll46xx_set_rate()
583 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | samsung_pll46xx_set_rate()
587 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | samsung_pll46xx_set_rate()
591 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; samsung_pll46xx_set_rate()
594 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | samsung_pll46xx_set_rate()
609 __raw_writel(con0, pll->con_reg); samsung_pll46xx_set_rate()
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| /linux-4.4.14/drivers/video/fbdev/ |
| H A D | pxa168fb.h | 356 #define CFG_COS0(con0) (con0)
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| /linux-4.4.14/drivers/video/fbdev/mmp/hw/ |
| H A D | mmp_ctrl.h | 599 #define CFG_COS0(con0) (con0)
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