Searched refs:cns3xxx_tmr1 (Results 1 - 1 of 1) sorted by relevance
| /linux-4.4.14/arch/arm/mach-cns3xxx/ |
| H A D | core.c | 114 static void __iomem *cns3xxx_tmr1; variable
118 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_shutdown()
124 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_set_oneshot()
128 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_set_oneshot()
134 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_set_periodic()
139 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_set_periodic()
141 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_set_periodic()
148 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_timer_set_next_event()
150 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_timer_set_next_event()
151 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_timer_set_next_event()
183 u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; cns3xxx_timer_interrupt()
214 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
216 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); __cns3xxx_timer_init()
219 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); __cns3xxx_timer_init()
220 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); __cns3xxx_timer_init()
222 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); __cns3xxx_timer_init()
223 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); __cns3xxx_timer_init()
226 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); __cns3xxx_timer_init()
229 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); __cns3xxx_timer_init()
232 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
234 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
237 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); __cns3xxx_timer_init()
238 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); __cns3xxx_timer_init()
241 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); __cns3xxx_timer_init()
243 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); __cns3xxx_timer_init()
246 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
248 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
258 cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); cns3xxx_timer_init()
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