Searched refs:cm_base (Results 1 - 10 of 10) sorted by relevance

/linux-4.4.14/arch/arm/mach-integrator/
H A Dcore.c37 static void __iomem *cm_base; variable
44 return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); cm_get()
58 val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; cm_control()
59 writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); cm_control()
66 writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + cm_clear_irqs()
83 cm_base = of_iomap(cm, 0); cm_init()
84 if (!cm_base) { cm_init()
/linux-4.4.14/drivers/clk/versatile/
H A Dclk-versatile.c23 static void __iomem *cm_base; variable
65 if (!cm_base) { cm_osc_setup()
74 cm_base = of_iomap(parent, 0); cm_osc_setup()
75 if (!cm_base) { cm_osc_setup()
82 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base); cm_osc_setup()
/linux-4.4.14/drivers/cpufreq/
H A Dintegrator-cpufreq.c25 static void __iomem *cm_base; variable
99 cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); integrator_set_target()
126 cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); integrator_set_target()
136 __raw_writel(0xa05f, cm_base + INTEGRATOR_HDR_LOCK_OFFSET); integrator_set_target()
137 __raw_writel(cm_osc, cm_base + INTEGRATOR_HDR_OSC_OFFSET); integrator_set_target()
138 __raw_writel(0, cm_base + INTEGRATOR_HDR_LOCK_OFFSET); integrator_set_target()
163 cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); integrator_get()
207 cm_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); integrator_cpufreq_probe()
208 if (!cm_base) integrator_cpufreq_probe()
/linux-4.4.14/arch/arm/mach-omap2/
H A Dcm_common.c34 /* cm_base: base virtual address of the CM IP block */
35 void __iomem *cm_base; variable
52 cm_base = cm; omap2_set_globals_cm()
251 * IVA2 offset is a negative value, must offset the cm_base address
328 cm_base = mem + data->offset; omap2_cm_base_init()
338 (cm_base && cm2_base))) omap2_cm_base_init()
H A Dcm2xxx_3xxx.h55 return readl_relaxed(cm_base + module + idx); omap2_cm_read_mod_reg()
60 writel_relaxed(val, cm_base + module + idx); omap2_cm_write_mod_reg()
H A Dcm2xxx.c215 if (idlest_reg < cm_base || idlest_reg > (cm_base + 0x0fff)) omap2xxx_cm_split_idlest_reg()
229 offs = idlest_reg - cm_base; omap2xxx_cm_split_idlest_reg()
H A Dcm.h26 extern void __iomem *cm_base;
H A Dcm3xxx.c129 if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) || omap3xxx_cm_split_idlest_reg()
130 idlest_reg > (cm_base + 0x1ffff)) omap3xxx_cm_split_idlest_reg()
144 offs = idlest_reg - cm_base; omap3xxx_cm_split_idlest_reg()
676 omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD); omap3xxx_cm_init()
H A Dcm33xx.c53 return readl_relaxed(cm_base + inst + idx); am33xx_cm_read_reg()
59 writel_relaxed(val, cm_base + inst + idx); am33xx_cm_write_reg()
H A Dcminst44xx.c69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; omap_cm_base_init()

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