Searched refs:clk_pol (Results 1 – 17 of 17) sorted by relevance
91 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,98 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,105 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
115 unsigned int clk_pol : 1; member137 unsigned int clk_pol : 1; member164 unsigned int clk_pol : 1; member
5 unsigned int clk_pol:1; member
39 int clk_pol; member
532 u8 serial, u8 clk_pol, u8 clk_gated) in lgs8gxx_set_mpeg_mode() argument544 t |= clk_pol ? TS_CLK_INVERTED : TS_CLK_NORMAL; in lgs8gxx_set_mpeg_mode()
1586 stv0367ter_set_clk_pol(state, state->config->clk_pol); in stv0367ter_init()2807 switch (state->config->clk_pol) { in stv0367cab_init()
52 unsigned int clk_pol:1; member
451 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT; in omap3isp_configure_bridge()2178 buscfg->bus.parallel.clk_pol = in isp_of_parse_node()
38 unsigned clk_pol:1; /* true = rising edge */ member
357 if (mt9v032->pdata && mt9v032->pdata->clk_pol) { in __mt9v032_set_power()922 pdata->clk_pol = !!(endpoint.bus.parallel.flags & in mt9v032_get_pdata()
290 if (pdata->clk_pol) { in mt9t001_s_stream()
176 sig_cfg.clk_pol = 0; in ipu_crtc_mode_set()
129 unsigned clk_pol:1; /* true = rising edge */ member604 sig.clk_pol << DI_D3_CLK_POL_SHIFT | in sdc_init_panel()836 sig_cfg.clk_pol = true; in __set_par()
972 rec_cfg.clk_pol = regk_sser_neg; in sync_serial_ioctl_unlocked()974 rec_cfg.clk_pol = regk_sser_pos; in sync_serial_ioctl_unlocked()1011 rec_cfg.clk_pol = regk_sser_neg; in sync_serial_ioctl_unlocked()
625 if (sig->clk_pol) in ipu_di_init_sync_panel()
824 .clk_pol = 0,831 .clk_pol = 0,