| H A D | cgu.c | 82 const struct ingenic_cgu_clk_info *clk_info; ingenic_pll_recalc_rate() local
89 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_pll_recalc_rate()
90 BUG_ON(clk_info->type != CGU_CLK_PLL); ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; ingenic_pll_recalc_rate()
123 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, ingenic_pll_calc() argument
130 pll_info = &clk_info->pll; ingenic_pll_calc()
138 n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); ingenic_pll_calc()
142 m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); ingenic_pll_calc()
161 const struct ingenic_cgu_clk_info *clk_info; ingenic_pll_round_rate() local
163 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_pll_round_rate()
164 BUG_ON(clk_info->type != CGU_CLK_PLL); ingenic_pll_round_rate()
166 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); ingenic_pll_round_rate()
176 const struct ingenic_cgu_clk_info *clk_info; ingenic_pll_set_rate() local
182 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_pll_set_rate()
183 BUG_ON(clk_info->type != CGU_CLK_PLL); ingenic_pll_set_rate()
184 pll_info = &clk_info->pll; ingenic_pll_set_rate()
186 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, ingenic_pll_set_rate()
190 clk_info->name, req_rate, rate); ingenic_pll_set_rate()
239 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_get_parent() local
243 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_get_parent()
245 if (clk_info->type & CGU_CLK_MUX) { ingenic_clk_get_parent()
246 reg = readl(cgu->base + clk_info->mux.reg); ingenic_clk_get_parent()
247 hw_idx = (reg >> clk_info->mux.shift) & ingenic_clk_get_parent()
248 GENMASK(clk_info->mux.bits - 1, 0); ingenic_clk_get_parent()
255 if (clk_info->parents[i] != -1) ingenic_clk_get_parent()
267 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_set_parent() local
272 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_set_parent()
274 if (clk_info->type & CGU_CLK_MUX) { ingenic_clk_set_parent()
279 * clk_info->parents which does not equal -1. ingenic_clk_set_parent()
282 num_poss = 1 << clk_info->mux.bits; ingenic_clk_set_parent()
284 if (clk_info->parents[hw_idx] == -1) ingenic_clk_set_parent()
294 mask = GENMASK(clk_info->mux.bits - 1, 0); ingenic_clk_set_parent()
295 mask <<= clk_info->mux.shift; ingenic_clk_set_parent()
300 reg = readl(cgu->base + clk_info->mux.reg); ingenic_clk_set_parent()
302 reg |= hw_idx << clk_info->mux.shift; ingenic_clk_set_parent()
303 writel(reg, cgu->base + clk_info->mux.reg); ingenic_clk_set_parent()
317 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_recalc_rate() local
321 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_recalc_rate()
323 if (clk_info->type & CGU_CLK_DIV) { ingenic_clk_recalc_rate()
324 div_reg = readl(cgu->base + clk_info->div.reg); ingenic_clk_recalc_rate()
325 div = (div_reg >> clk_info->div.shift) & ingenic_clk_recalc_rate()
326 GENMASK(clk_info->div.bits - 1, 0); ingenic_clk_recalc_rate()
336 ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info, ingenic_clk_calc_div() argument
345 div = min_t(unsigned, div, 1 << clk_info->div.bits); ingenic_clk_calc_div()
357 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_round_rate() local
360 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_round_rate()
362 if (clk_info->type & CGU_CLK_DIV) ingenic_clk_round_rate()
363 rate /= ingenic_clk_calc_div(clk_info, *parent_rate, req_rate); ingenic_clk_round_rate()
364 else if (clk_info->type & CGU_CLK_FIXDIV) ingenic_clk_round_rate()
365 rate /= clk_info->fixdiv.div; ingenic_clk_round_rate()
376 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_set_rate() local
383 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_set_rate()
385 if (clk_info->type & CGU_CLK_DIV) { ingenic_clk_set_rate()
386 div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate); ingenic_clk_set_rate()
393 reg = readl(cgu->base + clk_info->div.reg); ingenic_clk_set_rate()
396 mask = GENMASK(clk_info->div.bits - 1, 0); ingenic_clk_set_rate()
397 reg &= ~(mask << clk_info->div.shift); ingenic_clk_set_rate()
398 reg |= (div - 1) << clk_info->div.shift; ingenic_clk_set_rate()
401 if (clk_info->div.stop_bit != -1) ingenic_clk_set_rate()
402 reg &= ~BIT(clk_info->div.stop_bit); ingenic_clk_set_rate()
405 if (clk_info->div.ce_bit != -1) ingenic_clk_set_rate()
406 reg |= BIT(clk_info->div.ce_bit); ingenic_clk_set_rate()
409 writel(reg, cgu->base + clk_info->div.reg); ingenic_clk_set_rate()
412 if (clk_info->div.busy_bit != -1) { ingenic_clk_set_rate()
414 reg = readl(cgu->base + clk_info->div.reg); ingenic_clk_set_rate()
415 if (!(reg & BIT(clk_info->div.busy_bit))) ingenic_clk_set_rate()
434 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_enable() local
437 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_enable()
439 if (clk_info->type & CGU_CLK_GATE) { ingenic_clk_enable()
442 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); ingenic_clk_enable()
453 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_disable() local
456 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_disable()
458 if (clk_info->type & CGU_CLK_GATE) { ingenic_clk_disable()
461 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); ingenic_clk_disable()
470 const struct ingenic_cgu_clk_info *clk_info; ingenic_clk_is_enabled() local
474 clk_info = &cgu->clock_info[ingenic_clk->idx]; ingenic_clk_is_enabled()
476 if (clk_info->type & CGU_CLK_GATE) { ingenic_clk_is_enabled()
478 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); ingenic_clk_is_enabled()
504 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; ingenic_register_clock() local
512 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); ingenic_register_clock()
514 if (clk_info->type == CGU_CLK_EXT) { ingenic_register_clock()
515 clk = of_clk_get_by_name(cgu->np, clk_info->name); ingenic_register_clock()
518 __func__, clk_info->name); ingenic_register_clock()
522 err = clk_register_clkdev(clk, clk_info->name, NULL); ingenic_register_clock()
531 if (!clk_info->type) { ingenic_register_clock()
533 clk_info->name); ingenic_register_clock()
547 clk_init.name = clk_info->name; ingenic_register_clock()
551 caps = clk_info->type; ingenic_register_clock()
557 num_possible = 1 << clk_info->mux.bits; ingenic_register_clock()
559 num_possible = ARRAY_SIZE(clk_info->parents); ingenic_register_clock()
562 if (clk_info->parents[i] == -1) ingenic_register_clock()
565 parent = cgu->clocks.clks[clk_info->parents[i]]; ingenic_register_clock()
574 BUG_ON(clk_info->parents[0] == -1); ingenic_register_clock()
576 parent = cgu->clocks.clks[clk_info->parents[0]]; ingenic_register_clock()
581 clk_init.ops = clk_info->custom.clk_ops; ingenic_register_clock()
629 clk_info->name); ingenic_register_clock()
634 err = clk_register_clkdev(clk, clk_info->name, NULL); ingenic_register_clock()
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