Searched refs:clk_div_reg (Results 1 – 1 of 1) sorted by relevance
706 unsigned int clk_div_reg = 0; in sirfsoc_uart_set_termios() local799 clk_div_reg = baudrate_to_regv[ic].reg_val; in sirfsoc_uart_set_termios()803 if (unlikely(clk_div_reg == 0)) in sirfsoc_uart_set_termios()804 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate, in sirfsoc_uart_set_termios()806 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg); in sirfsoc_uart_set_termios()808 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate, in sirfsoc_uart_set_termios()811 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) / in sirfsoc_uart_set_termios()816 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK) in sirfsoc_uart_set_termios()838 len_val |= (((clk_div_reg & 0xc00) >> 10) << in sirfsoc_uart_set_termios()847 len_val |= (((clk_div_reg & 0xf000) >> 12) << in sirfsoc_uart_set_termios()