Searched refs:cik (Results 1 – 6 of 6) sorted by relevance
2350 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()2351 rdev->config.cik.max_shader_engines; in cik_tiling_mode_table_init()2353 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_tiling_mode_table_init()2366 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()2497 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2590 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2720 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2813 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2944 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()3074 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()[all …]
281 *value = rdev->config.cik.tile_config; in radeon_info_ioctl()335 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()336 rdev->config.cik.max_shader_engines; in radeon_info_ioctl()355 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()375 *value = rdev->config.cik.backend_map; in radeon_info_ioctl()404 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()430 *value = rdev->config.cik.max_shader_engines; in radeon_info_ioctl()442 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()477 value = rdev->config.cik.tile_mode_array; in radeon_info_ioctl()489 value = rdev->config.cik.macrotile_mode_array; in radeon_info_ioctl()[all …]
79 si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
1285 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()1341 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
803 struct cik_irq_stat_regs cik; member2205 struct cik_asic cik; member
25 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \