Searched refs:cfgcr2 (Results 1 - 4 of 4) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/i915/ |
| H A D | intel_ddi.c | 1566 uint32_t ctrl1, cfgcr1, cfgcr2; skl_ddi_pll_select() local
1588 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | skl_ddi_pll_select()
1607 cfgcr1 = cfgcr2 = 0; skl_ddi_pll_select()
1616 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; skl_ddi_pll_select()
2565 u32 ctl, cfgcr1, cfgcr2; member in struct:skl_dpll_regs
2574 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2580 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2586 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2610 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); skl_ddi_pll_enable()
2612 POSTING_READ(regs[pll->id].cfgcr2); skl_ddi_pll_enable()
2657 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); skl_ddi_pll_get_hw_state()
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| H A D | i915_drv.h | 384 uint32_t cfgcr1, cfgcr2; member in struct:intel_dpll_hw_state
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| H A D | intel_dp.c | 1121 pipe_config->dpll_hw_state.cfgcr2 = 0; skl_edp_set_pll_config()
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| H A D | intel_display.c | 12079 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", intel_dump_pipe_config()
12083 pipe_config->dpll_hw_state.cfgcr2); intel_dump_pipe_config()
12617 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); intel_pipe_config_compare()
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