Searched refs:ccm_base (Results 1 - 7 of 7) sorted by relevance

/linux-4.4.14/drivers/clk/imx/
H A Dclk-imx51-imx53.c33 #define MXC_CCM_CCR (ccm_base + 0x00)
34 #define MXC_CCM_CCDR (ccm_base + 0x04)
35 #define MXC_CCM_CSR (ccm_base + 0x08)
36 #define MXC_CCM_CCSR (ccm_base + 0x0c)
37 #define MXC_CCM_CACRR (ccm_base + 0x10)
38 #define MXC_CCM_CBCDR (ccm_base + 0x14)
39 #define MXC_CCM_CBCMR (ccm_base + 0x18)
40 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
41 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
42 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)
43 #define MXC_CCM_CS1CDR (ccm_base + 0x28)
44 #define MXC_CCM_CS2CDR (ccm_base + 0x2c)
45 #define MXC_CCM_CDCDR (ccm_base + 0x30)
46 #define MXC_CCM_CHSCDR (ccm_base + 0x34)
47 #define MXC_CCM_CSCDR2 (ccm_base + 0x38)
48 #define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
49 #define MXC_CCM_CSCDR4 (ccm_base + 0x40)
50 #define MXC_CCM_CWDR (ccm_base + 0x44)
51 #define MXC_CCM_CDHIPR (ccm_base + 0x48)
52 #define MXC_CCM_CDCR (ccm_base + 0x4c)
53 #define MXC_CCM_CTOR (ccm_base + 0x50)
54 #define MXC_CCM_CLPCR (ccm_base + 0x54)
55 #define MXC_CCM_CISR (ccm_base + 0x58)
56 #define MXC_CCM_CIMR (ccm_base + 0x5c)
57 #define MXC_CCM_CCOSR (ccm_base + 0x60)
58 #define MXC_CCM_CGPR (ccm_base + 0x64)
59 #define MXC_CCM_CCGR0 (ccm_base + 0x68)
60 #define MXC_CCM_CCGR1 (ccm_base + 0x6c)
61 #define MXC_CCM_CCGR2 (ccm_base + 0x70)
62 #define MXC_CCM_CCGR3 (ccm_base + 0x74)
63 #define MXC_CCM_CCGR4 (ccm_base + 0x78)
64 #define MXC_CCM_CCGR5 (ccm_base + 0x7c)
65 #define MXC_CCM_CCGR6 (ccm_base + 0x80)
66 #define MXC_CCM_CCGR7 (ccm_base + 0x84)
147 static void __init mx5_clocks_common_init(void __iomem *ccm_base) mx5_clocks_common_init() argument
333 void __iomem *ccm_base; mx50_clocks_init() local
349 ccm_base = of_iomap(np, 0); mx50_clocks_init()
350 WARN_ON(!ccm_base); mx50_clocks_init()
352 mx5_clocks_common_init(ccm_base); mx50_clocks_init()
395 void __iomem *ccm_base; mx51_clocks_init() local
411 ccm_base = of_iomap(np, 0); mx51_clocks_init()
412 WARN_ON(!ccm_base); mx51_clocks_init()
414 mx5_clocks_common_init(ccm_base); mx51_clocks_init()
484 void __iomem *ccm_base; mx53_clocks_init() local
504 ccm_base = of_iomap(np, 0); mx53_clocks_init()
505 WARN_ON(!ccm_base); mx53_clocks_init()
507 mx5_clocks_common_init(ccm_base); mx53_clocks_init()
H A Dclk-vf610.c17 #define CCM_CCR (ccm_base + 0x00)
18 #define CCM_CSR (ccm_base + 0x04)
19 #define CCM_CCSR (ccm_base + 0x08)
20 #define CCM_CACRR (ccm_base + 0x0c)
21 #define CCM_CSCMR1 (ccm_base + 0x10)
22 #define CCM_CSCDR1 (ccm_base + 0x14)
23 #define CCM_CSCDR2 (ccm_base + 0x18)
24 #define CCM_CSCDR3 (ccm_base + 0x1c)
25 #define CCM_CSCMR2 (ccm_base + 0x20)
26 #define CCM_CSCDR4 (ccm_base + 0x24)
27 #define CCM_CLPCR (ccm_base + 0x2c)
28 #define CCM_CISR (ccm_base + 0x30)
29 #define CCM_CIMR (ccm_base + 0x34)
30 #define CCM_CGPR (ccm_base + 0x3c)
31 #define CCM_CCGR0 (ccm_base + 0x40)
32 #define CCM_CCGR1 (ccm_base + 0x44)
33 #define CCM_CCGR2 (ccm_base + 0x48)
34 #define CCM_CCGR3 (ccm_base + 0x4c)
35 #define CCM_CCGR4 (ccm_base + 0x50)
36 #define CCM_CCGR5 (ccm_base + 0x54)
37 #define CCM_CCGR6 (ccm_base + 0x58)
38 #define CCM_CCGR7 (ccm_base + 0x5c)
39 #define CCM_CCGR8 (ccm_base + 0x60)
40 #define CCM_CCGR9 (ccm_base + 0x64)
41 #define CCM_CCGR10 (ccm_base + 0x68)
42 #define CCM_CCGR11 (ccm_base + 0x6c)
43 #define CCM_CMEOR0 (ccm_base + 0x70)
44 #define CCM_CMEOR1 (ccm_base + 0x74)
45 #define CCM_CMEOR2 (ccm_base + 0x78)
46 #define CCM_CMEOR3 (ccm_base + 0x7c)
47 #define CCM_CMEOR4 (ccm_base + 0x80)
48 #define CCM_CMEOR5 (ccm_base + 0x84)
49 #define CCM_CPPDSR (ccm_base + 0x88)
50 #define CCM_CCOWR (ccm_base + 0x8c)
51 #define CCM_CCPGR0 (ccm_base + 0x90)
52 #define CCM_CCPGR1 (ccm_base + 0x94)
53 #define CCM_CCPGR2 (ccm_base + 0x98)
54 #define CCM_CCPGR3 (ccm_base + 0x9c)
71 static void __iomem *ccm_base; variable
160 ccm_base = of_iomap(np, 0); vf610_clocks_init()
161 BUG_ON(!ccm_base); vf610_clocks_init()
H A Dclk-imx6sl.c104 static void __iomem *ccm_base; variable
135 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { imx6sl_get_arm_divider_for_wait()
176 saved_arm_div = readl_relaxed(ccm_base + CACRR); imx6sl_set_wait_clk()
177 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); imx6sl_set_wait_clk()
179 writel_relaxed(saved_arm_div, ccm_base + CACRR); imx6sl_set_wait_clk()
181 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) imx6sl_set_wait_clk()
295 ccm_base = base; imx6sl_clocks_init()
H A Dclk-imx25.c54 #define ccm(x) (ccm_base + (x))
100 void __iomem *ccm_base) __mx25_clocks_init()
102 BUG_ON(!ccm_base); __mx25_clocks_init()
99 __mx25_clocks_init(unsigned long osc_rate, void __iomem *ccm_base) __mx25_clocks_init() argument
/linux-4.4.14/arch/arm/mach-imx/
H A Dpm-imx6.c67 static void __iomem *ccm_base; variable
213 struct imx6_pm_base ccm_base; member in struct:imx6_cpu_pm_info
222 u32 val = readl_relaxed(ccm_base + CGPR); imx6q_set_int_mem_clk_lpm()
227 writel_relaxed(val, ccm_base + CGPR); imx6q_set_int_mem_clk_lpm()
241 val = readl_relaxed(ccm_base + CCR); imx6_enable_rbc()
244 writel_relaxed(val, ccm_base + CCR); imx6_enable_rbc()
247 val = readl_relaxed(ccm_base + CCR); imx6_enable_rbc()
250 writel(val, ccm_base + CCR); imx6_enable_rbc()
268 val = readl_relaxed(ccm_base + CLPCR); imx6q_enable_wb()
271 writel_relaxed(val, ccm_base + CLPCR); imx6q_enable_wb()
274 val = readl_relaxed(ccm_base + CCR); imx6q_enable_wb()
277 writel_relaxed(val, ccm_base + CCR); imx6q_enable_wb()
282 u32 val = readl_relaxed(ccm_base + CLPCR); imx6_set_lpm()
339 writel_relaxed(val, ccm_base + CLPCR); imx6_set_lpm()
509 pm_info->ccm_base.vbase = ccm_base; imx6q_suspend_init()
583 WARN_ON(!ccm_base); imx6_pm_common_init()
611 ccm_base = of_iomap(np, 0); imx6_pm_ccm_init()
612 BUG_ON(!ccm_base); imx6_pm_ccm_init()
618 val = readl_relaxed(ccm_base + CLPCR); imx6_pm_ccm_init()
620 writel_relaxed(val, ccm_base + CLPCR); imx6_pm_ccm_init()
H A Dpm-imx5.c139 static void __iomem *ccm_base; variable
158 ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) & mx5_cpu_lp_set()
200 __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); mx5_cpu_lp_set()
392 ccm_base = ioremap(data->ccm_addr, SZ_16K); imx5_pm_common_init()
395 WARN_ON(!ccm_base || !cortex_base || !gpc_base); imx5_pm_common_init()
/linux-4.4.14/crypto/
H A Dccm.c566 "ccm_base(%s,%s)", ctr->cra_driver_name, crypto_ccm_create_common()
651 if (snprintf(full_name, CRYPTO_MAX_ALG_NAME, "ccm_base(%s,%s)", crypto_ccm_base_create()
660 .name = "ccm_base",
938 MODULE_ALIAS_CRYPTO("ccm_base");

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