Searched refs:bpc (Results 1 - 66 of 66) sorted by relevance

/linux-4.4.14/arch/m32r/mm/
H A Dextable.c12 fixup = search_exception_tables(regs->bpc); fixup_exception()
14 regs->bpc = fixup->fixup; fixup_exception()
H A Dfault-nommu.c85 printk(" printing bpc:\n"); do_page_fault()
86 printk(KERN_ALERT "bpc = %08lx\n", regs->bpc); do_page_fault()
H A Dmmu.S82 mvfc r1, bpc
222 mvfc r2, bpc ; r2: bpc
229 mv r0, r2 ; address = bpc;
H A Dfault.c255 printk(KERN_ALERT " printing bpc:\n"); do_page_fault()
256 printk("%08lx\n", regs->bpc); do_page_fault()
/linux-4.4.14/drivers/gpu/drm/panel/
H A Dpanel-simple.c45 unsigned int bpc; member in struct:panel_desc
137 connector->display_info.bpc = panel->desc->bpc; panel_simple_get_fixed_modes()
389 .bpc = 6,
413 .bpc = 6,
436 .bpc = 6,
460 .bpc = 6,
483 .bpc = 6,
506 .bpc = 6,
529 .bpc = 6,
557 .bpc = 8,
585 .bpc = 6,
608 .bpc = 6,
632 .bpc = 6,
656 .bpc = 6,
679 .bpc = 8,
703 .bpc = 8,
732 .bpc = 6,
756 .bpc = 6,
780 .bpc = 6,
804 .bpc = 8,
828 .bpc = 6,
852 .bpc = 6,
875 .bpc = 6,
898 .bpc = 6,
921 .bpc = 16,
945 .bpc = 8,
968 .bpc = 8,
992 .bpc = 6,
1022 .bpc = 8,
1046 .bpc = 6,
1069 .bpc = 6,
1255 .bpc = 8,
1283 .bpc = 8,
1311 .bpc = 8,
1339 .bpc = 8,
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_connectors.c109 int bpc = 8; amdgpu_connector_get_monitor_bpc() local
117 if (connector->display_info.bpc) amdgpu_connector_get_monitor_bpc()
118 bpc = connector->display_info.bpc; amdgpu_connector_get_monitor_bpc()
125 if (connector->display_info.bpc) amdgpu_connector_get_monitor_bpc()
126 bpc = connector->display_info.bpc; amdgpu_connector_get_monitor_bpc()
134 if (connector->display_info.bpc) amdgpu_connector_get_monitor_bpc()
135 bpc = connector->display_info.bpc; amdgpu_connector_get_monitor_bpc()
140 if (connector->display_info.bpc) amdgpu_connector_get_monitor_bpc()
141 bpc = connector->display_info.bpc; amdgpu_connector_get_monitor_bpc()
150 bpc = 6; amdgpu_connector_get_monitor_bpc()
152 bpc = 8; amdgpu_connector_get_monitor_bpc()
159 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make amdgpu_connector_get_monitor_bpc()
160 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at amdgpu_connector_get_monitor_bpc()
161 * 12 bpc is always supported on hdmi deep color sinks, as this is amdgpu_connector_get_monitor_bpc()
162 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. amdgpu_connector_get_monitor_bpc()
164 if (bpc > 12) { amdgpu_connector_get_monitor_bpc()
165 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", amdgpu_connector_get_monitor_bpc()
166 connector->name, bpc); amdgpu_connector_get_monitor_bpc()
167 bpc = 12; amdgpu_connector_get_monitor_bpc()
181 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ amdgpu_connector_get_monitor_bpc()
182 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { amdgpu_connector_get_monitor_bpc()
185 bpc = 10; amdgpu_connector_get_monitor_bpc()
187 bpc = 8; amdgpu_connector_get_monitor_bpc()
189 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", amdgpu_connector_get_monitor_bpc()
190 connector->name, bpc); amdgpu_connector_get_monitor_bpc()
193 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { amdgpu_connector_get_monitor_bpc()
194 bpc = 8; amdgpu_connector_get_monitor_bpc()
195 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", amdgpu_connector_get_monitor_bpc()
196 connector->name, bpc); amdgpu_connector_get_monitor_bpc()
198 } else if (bpc > 8) { amdgpu_connector_get_monitor_bpc()
200 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", amdgpu_connector_get_monitor_bpc()
202 bpc = 8; amdgpu_connector_get_monitor_bpc()
206 if ((amdgpu_deep_color == 0) && (bpc > 8)) { amdgpu_connector_get_monitor_bpc()
209 bpc = 8; amdgpu_connector_get_monitor_bpc()
212 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", amdgpu_connector_get_monitor_bpc()
213 connector->name, connector->display_info.bpc, bpc); amdgpu_connector_get_monitor_bpc()
215 return bpc; amdgpu_connector_get_monitor_bpc()
H A Datombios_crtc.c317 int bpc = amdgpu_crtc->bpc; amdgpu_atombios_crtc_adjust_pll() local
358 switch (bpc) { amdgpu_atombios_crtc_adjust_pll()
535 int bpc, amdgpu_atombios_crtc_program_pll()
604 switch (bpc) { amdgpu_atombios_crtc_program_pll()
635 switch (bpc) { amdgpu_atombios_crtc_program_pll()
678 amdgpu_crtc->bpc = 8; amdgpu_atombios_crtc_prepare_pll()
694 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector); amdgpu_atombios_crtc_prepare_pll()
753 (amdgpu_crtc->bpc > 8)) amdgpu_atombios_crtc_set_pll()
784 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); amdgpu_atombios_crtc_set_pll()
525 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) amdgpu_atombios_crtc_program_pll() argument
H A Datombios_crtc.h50 int bpc,
H A Ddce_v10_0.c716 int bpc = 0; dce_v10_0_program_fmt() local
722 bpc = amdgpu_connector_get_monitor_bpc(connector); dce_v10_0_program_fmt()
735 if (bpc == 0) dce_v10_0_program_fmt()
738 switch (bpc) { dce_v10_0_program_fmt()
1780 int bpc = 8; dce_v10_0_afmt_setmode() local
1789 /* hdmi deep color mode general control packets setup, if bpc > 8 */ dce_v10_0_afmt_setmode()
1792 bpc = amdgpu_crtc->bpc; dce_v10_0_afmt_setmode()
1808 switch (bpc) { dce_v10_0_afmt_setmode()
1816 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", dce_v10_0_afmt_setmode()
1817 connector->name, bpc); dce_v10_0_afmt_setmode()
1822 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", dce_v10_0_afmt_setmode()
1828 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", dce_v10_0_afmt_setmode()
1872 if (bpc > 8) dce_v10_0_afmt_setmode()
2154 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce_v10_0_crtc_do_set_base()
2165 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce_v10_0_crtc_do_set_base()
2216 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT dce_v10_0_crtc_do_set_base()
2217 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to dce_v10_0_crtc_do_set_base()
H A Ddce_v11_0.c704 int bpc = 0; dce_v11_0_program_fmt() local
710 bpc = amdgpu_connector_get_monitor_bpc(connector); dce_v11_0_program_fmt()
723 if (bpc == 0) dce_v11_0_program_fmt()
726 switch (bpc) { dce_v11_0_program_fmt()
1768 int bpc = 8; dce_v11_0_afmt_setmode() local
1777 /* hdmi deep color mode general control packets setup, if bpc > 8 */ dce_v11_0_afmt_setmode()
1780 bpc = amdgpu_crtc->bpc; dce_v11_0_afmt_setmode()
1796 switch (bpc) { dce_v11_0_afmt_setmode()
1804 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", dce_v11_0_afmt_setmode()
1805 connector->name, bpc); dce_v11_0_afmt_setmode()
1810 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", dce_v11_0_afmt_setmode()
1816 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", dce_v11_0_afmt_setmode()
1860 if (bpc > 8) dce_v11_0_afmt_setmode()
2142 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce_v11_0_crtc_do_set_base()
2153 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce_v11_0_crtc_do_set_base()
2204 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT dce_v11_0_crtc_do_set_base()
2205 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to dce_v11_0_crtc_do_set_base()
H A Ddce_v8_0.c664 int bpc = 0; dce_v8_0_program_fmt() local
670 bpc = amdgpu_connector_get_monitor_bpc(connector); dce_v8_0_program_fmt()
683 if (bpc == 0) dce_v8_0_program_fmt()
686 switch (bpc) { dce_v8_0_program_fmt()
1735 int bpc = 8; dce_v8_0_afmt_setmode() local
1745 /* hdmi deep color mode general control packets setup, if bpc > 8 */ dce_v8_0_afmt_setmode()
1748 bpc = amdgpu_crtc->bpc; dce_v8_0_afmt_setmode()
1766 switch (bpc) { dce_v8_0_afmt_setmode()
1772 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", dce_v8_0_afmt_setmode()
1773 connector->name, bpc); dce_v8_0_afmt_setmode()
1778 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", dce_v8_0_afmt_setmode()
1784 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", dce_v8_0_afmt_setmode()
1817 if (bpc > 8) dce_v8_0_afmt_setmode()
2085 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce_v8_0_crtc_do_set_base()
2095 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce_v8_0_crtc_do_set_base()
2140 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT dce_v8_0_crtc_do_set_base()
2141 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to dce_v8_0_crtc_do_set_base()
H A Datombios_dp.c245 /* get bpc from the EDID */ amdgpu_atombios_dp_convert_bpc_to_bpp()
246 static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc) amdgpu_atombios_dp_convert_bpc_to_bpp() argument
248 if (bpc == 0) amdgpu_atombios_dp_convert_bpc_to_bpp()
251 return bpc * 3; amdgpu_atombios_dp_convert_bpc_to_bpp()
H A Datombios_encoders.c352 int bpc = 8; amdgpu_atombios_encoder_get_bpc() local
356 bpc = amdgpu_crtc->bpc; amdgpu_atombios_encoder_get_bpc()
359 switch (bpc) { amdgpu_atombios_encoder_get_bpc()
H A Damdgpu_mode.h400 int bpc; member in struct:amdgpu_crtc
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_connectors.c131 int bpc = 8; radeon_get_monitor_bpc() local
139 if (connector->display_info.bpc) radeon_get_monitor_bpc()
140 bpc = connector->display_info.bpc; radeon_get_monitor_bpc()
147 if (connector->display_info.bpc) radeon_get_monitor_bpc()
148 bpc = connector->display_info.bpc; radeon_get_monitor_bpc()
156 if (connector->display_info.bpc) radeon_get_monitor_bpc()
157 bpc = connector->display_info.bpc; radeon_get_monitor_bpc()
162 if (connector->display_info.bpc) radeon_get_monitor_bpc()
163 bpc = connector->display_info.bpc; radeon_get_monitor_bpc()
172 bpc = 6; radeon_get_monitor_bpc()
174 bpc = 8; radeon_get_monitor_bpc()
181 if ((bpc > 8) && !ASIC_IS_DCE4(rdev)) { radeon_get_monitor_bpc()
182 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 8 bpc.\n", radeon_get_monitor_bpc()
183 connector->name, bpc); radeon_get_monitor_bpc()
184 bpc = 8; radeon_get_monitor_bpc()
188 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make radeon_get_monitor_bpc()
189 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at radeon_get_monitor_bpc()
190 * 12 bpc is always supported on hdmi deep color sinks, as this is radeon_get_monitor_bpc()
191 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. radeon_get_monitor_bpc()
193 if (bpc > 12) { radeon_get_monitor_bpc()
194 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", radeon_get_monitor_bpc()
195 connector->name, bpc); radeon_get_monitor_bpc()
196 bpc = 12; radeon_get_monitor_bpc()
210 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ radeon_get_monitor_bpc()
211 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { radeon_get_monitor_bpc()
214 bpc = 10; radeon_get_monitor_bpc()
216 bpc = 8; radeon_get_monitor_bpc()
218 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", radeon_get_monitor_bpc()
219 connector->name, bpc); radeon_get_monitor_bpc()
222 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { radeon_get_monitor_bpc()
223 bpc = 8; radeon_get_monitor_bpc()
224 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", radeon_get_monitor_bpc()
225 connector->name, bpc); radeon_get_monitor_bpc()
228 else if (bpc > 8) { radeon_get_monitor_bpc()
230 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", radeon_get_monitor_bpc()
232 bpc = 8; radeon_get_monitor_bpc()
236 if ((radeon_deep_color == 0) && (bpc > 8)) { radeon_get_monitor_bpc()
239 bpc = 8; radeon_get_monitor_bpc()
242 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", radeon_get_monitor_bpc()
243 connector->name, connector->display_info.bpc, bpc); radeon_get_monitor_bpc()
245 return bpc; radeon_get_monitor_bpc()
H A Devergreen_hdmi.c72 int bpc = 8; evergreen_hdmi_update_acr() local
76 bpc = radeon_crtc->bpc; evergreen_hdmi_update_acr()
79 if (bpc > 8) evergreen_hdmi_update_acr()
317 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) dce4_hdmi_set_color_depth() argument
328 switch (bpc) { dce4_hdmi_set_color_depth()
334 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", dce4_hdmi_set_color_depth()
335 connector->name, bpc); dce4_hdmi_set_color_depth()
340 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", dce4_hdmi_set_color_depth()
346 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", dce4_hdmi_set_color_depth()
H A Datombios_crtc.c565 int bpc = radeon_crtc->bpc; atombios_adjust_pll() local
649 switch (bpc) { atombios_adjust_pll()
824 int bpc, atombios_crtc_program_pll()
892 switch (bpc) { atombios_crtc_program_pll()
921 switch (bpc) { atombios_crtc_program_pll()
963 radeon_crtc->bpc = 8; atombios_crtc_prepare_pll()
981 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); atombios_crtc_prepare_pll()
1070 (radeon_crtc->bpc > 8)) atombios_crtc_set_pll()
1109 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); atombios_crtc_set_pll()
1242 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce4_crtc_do_set_base()
1252 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ dce4_crtc_do_set_base()
1387 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT dce4_crtc_do_set_base()
1388 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to dce4_crtc_do_set_base()
1554 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ avivo_crtc_do_set_base()
1598 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ avivo_crtc_do_set_base()
814 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) atombios_crtc_program_pll() argument
H A Dradeon_audio.h59 void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc);
H A Dradeon_audio.c91 u32 offset, int bpc);
653 int bpc = 8; radeon_hdmi_set_color_depth() local
662 bpc = radeon_crtc->bpc; radeon_hdmi_set_color_depth()
666 radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc); radeon_hdmi_set_color_depth()
H A Datombios_dp.c296 /* get bpc from the EDID */ convert_bpc_to_bpp()
297 static int convert_bpc_to_bpp(int bpc) convert_bpc_to_bpp() argument
299 if (bpc == 0) convert_bpc_to_bpp()
302 return bpc * 3; convert_bpc_to_bpp()
H A Dradeon_dp_mst.c371 if (radeon_connector->base.display_info.bpc) radeon_dp_mst_prepare_pll()
372 radeon_crtc->bpc = radeon_connector->base.display_info.bpc; radeon_dp_mst_prepare_pll()
374 radeon_crtc->bpc = 8; radeon_dp_mst_prepare_pll()
H A Drs600.c157 int bpc = 0; avivo_program_fmt() local
163 bpc = radeon_get_monitor_bpc(connector); avivo_program_fmt()
171 if (bpc == 0) avivo_program_fmt()
174 switch (bpc) { avivo_program_fmt()
H A Datombios_encoders.c454 int bpc = 8; radeon_atom_get_bpc() local
458 bpc = radeon_crtc->bpc; radeon_atom_get_bpc()
461 switch (bpc) { radeon_atom_get_bpc()
H A Devergreen.c1294 int bpc = 0; dce4_program_fmt() local
1300 bpc = radeon_get_monitor_bpc(connector); dce4_program_fmt()
1313 if (bpc == 0) dce4_program_fmt()
1316 switch (bpc) { dce4_program_fmt()
H A Dr600.c297 int bpc = 0; dce3_program_fmt() local
303 bpc = radeon_get_monitor_bpc(connector); dce3_program_fmt()
316 if (bpc == 0) dce3_program_fmt()
319 switch (bpc) { dce3_program_fmt()
H A Dradeon_mode.h360 int bpc; member in struct:radeon_crtc
H A Dcik.c9023 int bpc = 0; dce8_program_fmt() local
9029 bpc = radeon_get_monitor_bpc(connector); dce8_program_fmt()
9042 if (bpc == 0) dce8_program_fmt()
9045 switch (bpc) { dce8_program_fmt()
/linux-4.4.14/arch/m32r/kernel/
H A Dtraps.c199 if (regs->bpc < PAGE_OFFSET) show_registers()
204 if (__get_user(c, &((unsigned char*)regs->bpc)[i])) { show_registers()
275 DO_ERROR_INFO(0x20, SIGILL, "reserved instruction ", rie_handler, ILL_ILLOPC, regs->bpc)
276 DO_ERROR_INFO(0x100, SIGILL, "privileged instruction", pie_handler, ILL_PRVOPC, regs->bpc)
277 DO_ERROR_INFO(-1, SIGILL, "illegal trap", ill_trap, ILL_ILLTRP, regs->bpc)
296 if (copy_from_user(&insn, (void *)regs->bpc, 4)) { do_alignment_check()
312 if (copy_from_user(&insn, (void *)regs->bpc, 4)) { do_alignment_check()
H A Dsignal.c73 COPY(bpc); restore_sigcontext()
147 COPY(bpc); setup_sigcontext()
209 regs->bpc = (unsigned long)ksig->ka.sa.sa_handler; setup_rt_frame()
222 if (get_user(inst, (u16 __user *)(regs->bpc - 2))) prev_insn()
225 regs->bpc -= 2; prev_insn()
227 regs->bpc -= 4; prev_insn()
H A Dalign.c471 regs->bpc += 4; insn_check()
475 if (!(regs->bpc & 0x2) && insn & 0x8000) { insn_check()
477 regs->bpc += 4; insn_check()
480 regs->bpc += 2; insn_check()
574 if ((insn16 & 0x8000) && (regs->bpc & 3)) handle_unaligned_access()
H A Dprocess.c79 regs->bpc, regs->psw, regs->lr, regs->fp); show_regs()
H A Dentry.S47 * @(0x50,sp) - bpc
447 mvfc r2, bpc ; set address
H A Dptrace.c562 addr = (regs->bpc - 2) & ~3; withdraw_debug_trap()
563 regs->bpc -= 2; withdraw_debug_trap()
H A Dhead.S198 mvtc r4, bpc
/linux-4.4.14/arch/m32r/include/asm/
H A Dptrace.h33 #define instruction_pointer(regs) ((regs)->bpc)
H A Dassembler.h94 mvfc r13, bpc
174 mvtc r14, bpc
H A Dprocessor.h110 regs->bpc = new_pc; \
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_hdmi.c584 return connector->display_info.bpc > 8; hdmi_sink_is_deep_color()
618 /* phase information not relevant for 8bpc */ gcp_default_phase_possible()
1010 * for 12bpc with pixel repeat. ibx_enable_hdmi()
1052 * The procedure for 12bpc is as follows: cpt_enable_hdmi()
1054 * 2. enable HDMI with 8bpc cpt_enable_hdmi()
1055 * 3. enable HDMI with 12bpc cpt_enable_hdmi()
1203 /* check if we can do 8bpc */ intel_hdmi_mode_valid()
1206 /* if we can't do 8bpc we may still be able to do 12bpc */ intel_hdmi_mode_valid()
1239 * HDMI 12bpc affects the clocks, so it's only possible
1283 * HDMI is either 12 or 8, so if the display lets 10bpc sneak intel_hdmi_compute_config()
1284 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi intel_hdmi_compute_config()
1291 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); intel_hdmi_compute_config()
1294 /* Need to adjust the port link by 1.5x for 12bpc. */ intel_hdmi_compute_config()
1297 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); intel_hdmi_compute_config()
1304 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); intel_hdmi_compute_config()
H A Dintel_crt.c234 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ intel_crt_mode_valid()
250 /* LPT FDI RX only supports 8bpc. */ intel_crt_compute_config()
H A Dintel_display.c1995 * that in pipeconf reg. For HDMI we must use 8bpc ironlake_enable_pch_transcoder()
1996 * here for both 8bpc and 12bpc. ironlake_enable_pch_transcoder()
4199 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; ironlake_pch_enable() local
4206 temp |= bpc << 9; /* same format but at 11:9 */ ironlake_pch_enable()
7845 /* only g4x and later have fancy bpc/dither controls */ i9xx_set_pipeconf()
8671 * accuracy. Perhaps we even need to take the bpc value into intel_set_pipe_csc()
11925 /* Don't use an invalid EDID bpc value */ connected_sink_compute_bpp()
11926 if (connector->base.display_info.bpc && connected_sink_compute_bpp()
11927 connector->base.display_info.bpc * 3 < bpp) { connected_sink_compute_bpp()
11929 bpp, connector->base.display_info.bpc*3); connected_sink_compute_bpp()
11930 pipe_config->pipe_bpp = connector->base.display_info.bpc*3; connected_sink_compute_bpp()
11934 if (connector->base.display_info.bpc == 0) { connected_sink_compute_bpp()
12310 * only enable it on 6bpc panels. */
H A Dintel_drv.h431 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
H A Dintel_tv.c928 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n"); intel_tv_compute_config()
H A Dintel_sdvo.c1135 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); intel_sdvo_compute_config()
H A Dintel_dp.c1443 * bpc in between. */ intel_dp_compute_config()
1448 if (intel_connector->base.display_info.bpc == 0 && intel_dp_compute_config()
/linux-4.4.14/drivers/gpu/drm/msm/edp/
H A Dedp_connector.c88 if (connector->display_info.bpc > 8) edp_connector_mode_valid()
H A Dedp_ctrl.c1282 ctrl->color_depth = info->bpc; msm_edp_ctrl_timing_cfg()
/linux-4.4.14/arch/m32r/include/uapi/asm/
H A Dptrace.h100 unsigned long bpc; /* saved PC for TRAP syscalls */ member in struct:pt_regs
/linux-4.4.14/drivers/gpu/drm/
H A Ddrm_edid.c72 /* Force 8bpc */
74 /* Force 12bpc */
131 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
140 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
3589 * @info: Updated with maximum supported deep color bpc and color format
3618 /* HDMI supports at least 8 bpc */ for_each_cea_db()
3619 info->bpc = 8; for_each_cea_db()
3647 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", for_each_cea_db()
3649 info->bpc = dc_bpc; for_each_cea_db()
3706 info->bpc = 0; drm_add_display_info()
3737 info->bpc = 6; drm_add_display_info()
3740 info->bpc = 8; drm_add_display_info()
3743 info->bpc = 10; drm_add_display_info()
3746 info->bpc = 12; drm_add_display_info()
3749 info->bpc = 14; drm_add_display_info()
3752 info->bpc = 16; drm_add_display_info()
3756 info->bpc = 0; drm_add_display_info()
3760 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", drm_add_display_info()
3761 connector->name, info->bpc); drm_add_display_info()
3824 connector->display_info.bpc = 8; drm_add_edid_modes()
3827 connector->display_info.bpc = 12; drm_add_edid_modes()
/linux-4.4.14/drivers/gpu/drm/nouveau/
H A Dnouveau_connector.c705 if (nv_connector->edid && connector->display_info.bpc) nouveau_connector_detect_depth()
710 connector->display_info.bpc = 6; nouveau_connector_detect_depth()
714 /* we're out of options unless we're LVDS, default to 8bpc */ nouveau_connector_detect_depth()
716 connector->display_info.bpc = 8; nouveau_connector_detect_depth()
720 connector->display_info.bpc = 6; nouveau_connector_detect_depth()
725 connector->display_info.bpc = 8; nouveau_connector_detect_depth()
740 connector->display_info.bpc = 8; nouveau_connector_detect_depth()
864 clock = clock * (connector->display_info.bpc * 3) / 10; nouveau_connector_mode_valid()
H A Dnv50_display.c703 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) nv50_crtc_set_dither()
710 if (connector->display_info.bpc >= 8) nv50_crtc_set_dither()
1999 if (nv_connector->base.display_info.bpc == 8) nv50_sor_mode_set()
2006 if (nv_connector->base.display_info.bpc == 6) { nv50_sor_mode_set()
2010 if (nv_connector->base.display_info.bpc == 8) { nv50_sor_mode_set()
2188 switch (nv_connector->base.display_info.bpc) { nv50_pior_mode_set()
H A Dnouveau_display.c333 { 6, DITHERING_DEPTH_6BPC, "6 bpc" },
334 { 6, DITHERING_DEPTH_8BPC, "8 bpc" },
/linux-4.4.14/arch/mips/alchemy/common/
H A Dclock.c397 struct clk_hw *pc, *bpc, *free; alchemy_clk_fgcs_detr() local
403 bpc = NULL; alchemy_clk_fgcs_detr()
438 bpc = pc; alchemy_clk_fgcs_detr()
465 bpc = free; alchemy_clk_fgcs_detr()
477 req->best_parent_hw = bpc; alchemy_clk_fgcs_detr()
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5_encoder.c161 /* Get color format from panel, default is 8bpc */ mdp5_encoder_mode_set()
164 switch (connector->display_info.bpc) { mdp5_encoder_mode_set()
/linux-4.4.14/drivers/video/console/
H A Dsticore.c496 unsigned int size, bpc; sti_select_fbfont() local
511 bpc = ((fbfont->width+7)/8) * fbfont->height; sti_select_fbfont()
512 size = bpc * 256; sti_select_fbfont()
524 nf->bytes_per_char = bpc; sti_select_fbfont()
531 memcpy(dest, fbfont->data, bpc*256); sti_select_fbfont()
/linux-4.4.14/fs/ocfs2/
H A Dextent_map.c677 int bpc = ocfs2_clusters_to_blocks(inode->i_sb, 1); ocfs2_extent_map_get_blocks() local
695 boff += (v_blkno & (u64)(bpc - 1)); ocfs2_extent_map_get_blocks()
702 *ret_count -= v_blkno & (u64)(bpc - 1); ocfs2_extent_map_get_blocks()
H A Dxattr.c1090 u32 cpos, p_cluster, num_clusters, bpc, clusters; ocfs2_xattr_get_value_outside() local
1099 bpc = ocfs2_clusters_to_blocks(inode->i_sb, 1); ocfs2_xattr_get_value_outside()
1113 for (i = 0; i < num_clusters * bpc; i++, blkno++) { ocfs2_xattr_get_value_outside()
1339 u32 cpos = 0, bpc = ocfs2_clusters_to_blocks(inode->i_sb, 1); __ocfs2_xattr_set_value_outside() local
1361 for (i = 0; i < num_clusters * bpc; i++, blkno++) { __ocfs2_xattr_set_value_outside()
3958 u32 bpc = ocfs2_xattr_buckets_per_cluster(OCFS2_SB(inode->i_sb)); ocfs2_iterate_xattr_buckets() local
3959 u32 num_buckets = clusters * bpc; ocfs2_iterate_xattr_buckets()
5091 u16 bpc = ocfs2_clusters_to_blocks(inode->i_sb, 1); ocfs2_add_new_xattr_cluster() local
5126 if (bucket_blkno(first) + (prev_clusters * bpc) == block && ocfs2_add_new_xattr_cluster()
6922 unsigned int bpc = ocfs2_reflink_xattr_buckets() local
6942 reflink_buckets = min(num_buckets, bpc * num_clusters); ocfs2_reflink_xattr_buckets()
H A Dsuballoc.c1613 unsigned int bpc = le16_to_cpu(cl->cl_bpc); ocfs2_bg_discontig_fix_by_rec() local
1614 unsigned int bitoff = le32_to_cpu(rec->e_cpos) * bpc; ocfs2_bg_discontig_fix_by_rec()
1615 unsigned int bitcount = le16_to_cpu(rec->e_leaf_clusters) * bpc; ocfs2_bg_discontig_fix_by_rec()
/linux-4.4.14/drivers/video/fbdev/omap/
H A Dsossi.c368 static void sossi_set_bits_per_cycle(int bpc) sossi_set_bits_per_cycle() argument
377 switch (bpc) { sossi_set_bits_per_cycle()
H A Domapfb.h130 void (*set_bits_per_cycle)(int bpc);
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_lcdc_encoder.c118 bpp = 3 * connector->display_info.bpc; setup_phy()
/linux-4.4.14/drivers/gpu/drm/tegra/
H A Dsor.c1233 config.bits_per_pixel = output->connector.display_info.bpc * 3; tegra_sor_edp_enable()
2020 switch (info->bpc) { tegra_sor_hdmi_enable()
2030 WARN(1, "%u bits-per-color not supported\n", info->bpc); tegra_sor_hdmi_enable()
2061 switch (info->bpc) { tegra_sor_hdmi_enable()
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c418 encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) { nv04_dfp_mode_set()
/linux-4.4.14/drivers/net/ethernet/brocade/bna/
H A Dbna_enet.c198 bna_stats_copy(bpc, bpc); bna_bfi_stats_get_rsp()
/linux-4.4.14/arch/m68k/kernel/
H A Dhead.S2741 .byte 3,0xc0 /* receiver: 8 bpc */
2742 .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
2765 .byte 3,0xc0 /* receiver: 8 bpc */
2766 .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
/linux-4.4.14/include/drm/
H A Ddrm_crtc.h139 unsigned int bpc; member in struct:drm_display_info
/linux-4.4.14/tools/perf/util/
H A Devsel.c392 { "branch", "branches", "bpu", "btb", "bpc", },

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