| /linux-4.4.14/drivers/staging/fbtft/ |
| H A D | fb_hx8353d.c | 91 rgb/bgr: set_var()
93 rgb h/w pin for color filter setting: 0=rgb, 1=bgr set_var()
95 rgb-bgr order color filter panel: 0=rgb, 1=bgr */ set_var()
98 write_reg(par, 0x36, mx | my | (par->bgr << 3)); set_var()
101 write_reg(par, 0x36, my | mv | (par->bgr << 3)); set_var()
104 write_reg(par, 0x36, par->bgr << 3); set_var()
107 write_reg(par, 0x36, mx | mv | (par->bgr << 3)); set_var()
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| H A D | fb_ili9481.c | 73 write_reg(par, 0x36, ROWxCOL | HFLIP | VFLIP | (par->bgr << 3)); set_var()
76 write_reg(par, 0x36, VFLIP | (par->bgr << 3)); set_var()
79 write_reg(par, 0x36, ROWxCOL | (par->bgr << 3)); set_var()
82 write_reg(par, 0x36, HFLIP | (par->bgr << 3)); set_var()
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| H A D | fbtft_device.c | 74 static int bgr = -1; variable
75 module_param(bgr, int, 0);
76 MODULE_PARM_DESC(bgr,
283 .bgr = true,
304 .bgr = true,
323 .bgr = true,
343 .bgr = true,
418 .bgr = true,
439 .bgr = true,
460 .bgr = true,
551 .bgr = true,
590 .bgr = true,
611 .bgr = true,
633 .bgr = true,
654 .bgr = false,
686 .bgr = true,
704 .bgr = true,
724 .bgr = true,
744 .bgr = true,
812 .bgr = true,
831 .bgr = true,
853 .bgr = true,
870 .bgr = true,
897 .bgr = true,
917 .bgr = true,
957 .bgr = true,
977 .bgr = true,
999 .bgr = true,
1017 .bgr = true,
1067 .bgr = true,
1087 .bgr = true,
1107 .bgr = true,
1127 .bgr = true,
1166 .bgr = true,
1484 if (bgr == 0) fbtft_device_init()
1485 pdata->bgr = false; fbtft_device_init()
1486 else if (bgr == 1) fbtft_device_init()
1487 pdata->bgr = true; fbtft_device_init()
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| H A D | fb_ili9486.c | 73 write_reg(par, 0x36, 0x80 | (par->bgr << 3)); set_var()
76 write_reg(par, 0x36, 0x20 | (par->bgr << 3)); set_var()
79 write_reg(par, 0x36, 0x40 | (par->bgr << 3)); set_var()
82 write_reg(par, 0x36, 0xE0 | (par->bgr << 3)); set_var()
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| H A D | fb_ili9341.c | 100 write_reg(par, 0x36, (1 << MEM_X) | (par->bgr << MEM_BGR)); set_var()
104 (1 << MEM_V) | (1 << MEM_L) | (par->bgr << MEM_BGR)); set_var()
107 write_reg(par, 0x36, (1 << MEM_Y) | (par->bgr << MEM_BGR)); set_var()
111 (1 << MEM_V) | (par->bgr << MEM_BGR)); set_var()
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| H A D | fb_s6d02a1.c | 124 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); set_var()
127 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); set_var()
130 write_reg(par, 0x36, par->bgr << 3); set_var()
133 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); set_var()
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| H A D | fb_s6d1121.c | 111 write_reg(par, 0x03, 0x0003 | (par->bgr << 12)); set_var()
114 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); set_var()
117 write_reg(par, 0x03, 0x000A | (par->bgr << 12)); set_var()
120 write_reg(par, 0x03, 0x0009 | (par->bgr << 12)); set_var()
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| H A D | fb_st7735r.c | 117 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); set_var()
120 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); set_var()
123 write_reg(par, 0x36, par->bgr << 3); set_var()
126 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); set_var()
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| H A D | fb_hx8340bn.c | 119 write_reg(par, 0x36, par->bgr << 3); set_var()
122 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); set_var()
125 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); set_var()
128 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); set_var()
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| H A D | fb_ili9320.c | 203 write_reg(par, 0x3, (par->bgr << 12) | 0x30); set_var()
206 write_reg(par, 0x3, (par->bgr << 12) | 0x28); set_var()
209 write_reg(par, 0x3, (par->bgr << 12) | 0x00); set_var()
212 write_reg(par, 0x3, (par->bgr << 12) | 0x18); set_var()
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| H A D | fb_ili9325.c | 199 write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); set_var()
202 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); set_var()
205 write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); set_var()
208 write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); set_var()
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| H A D | fbtft.h | 72 * @set_var: Configure LCD with values from variables like @rotate and @bgr
147 * @bgr: LCD Controller BGR bit
158 bool bgr; member in struct:fbtft_platform_data
208 * @bgr: BGR mode/\n
250 bool bgr; member in struct:fbtft_par
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| H A D | fb_ili9340.c | 126 write_reg(par, 0x36, val | (par->bgr << 3)); set_var()
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| H A D | fb_hx8347d.c | 81 write_reg(par, 0x16, 0x60 | (par->bgr << 3)); init_display()
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| H A D | fb_hx8357d.c | 182 val |= (par->bgr ? HX8357D_MADCTL_RGB : HX8357D_MADCTL_BGR); set_var()
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| H A D | fb_ssd1289.c | 50 (1 << 13) | (par->bgr << 11) | (1 << 9) | (HEIGHT - 1)); init_display()
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| H A D | fb_ssd1331.c | 29 write_reg(par, 0xa0, 0x70 | (par->bgr << 2)); /* Set Colour Depth */ init_display()
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| H A D | fb_ssd1351.c | 79 remap = 0x60 | (par->bgr << 2); /* Set Colour Depth */ set_var()
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| H A D | fb_st7789v.c | 146 if (par->bgr) set_var()
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| H A D | fb_ili9163.c | 218 if (par->bgr) set_var()
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| H A D | fbtft-core.c | 804 par->bgr = pdata->bgr; fbtft_framebuffer_alloc()
1299 pdata->bgr = of_property_read_bool(node, "bgr"); fbtft_probe_dt()
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| /linux-4.4.14/drivers/video/fbdev/ |
| H A D | amba-clcd.c | 239 bool bgr, rgb; clcdfb_set_bitfields() local
241 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0; clcdfb_set_bitfields()
244 if (!bgr && !rgb) clcdfb_set_bitfields()
250 bgr = caps & CLCD_CAP_BGR; clcdfb_set_bitfields()
252 if (bgr) { clcdfb_set_bitfields()
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| H A D | bf537-lq035.c | 63 static int bgr; variable
64 module_param(bgr, int, 0);
65 MODULE_PARM_DESC(bgr,
748 if (bgr) { bfin_lq035_probe()
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| H A D | sm501fb.c | 95 int swap_endian; /* set to swap rgb=>bgr */
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| /linux-4.4.14/drivers/tty/serial/ |
| H A D | sunsab.h | 62 u8 bgr; /* Baud Rate Generator Register */ member in struct:sab82532_async_wr_regs
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| H A D | sunsab.c | 428 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); sunsab_tx_idle()
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| /linux-4.4.14/drivers/media/platform/vivid/ |
| H A D | vivid-vid-common.c | 307 .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
|