Searched refs:banks (Results 1 - 200 of 226) sorted by relevance

12

/linux-4.4.14/arch/arm/mach-davinci/
H A Dasp.h7 /* Bases of dm644x and dm355 register banks */
11 /* Bases of dm365 register banks */
14 /* Bases of dm646x register banks */
18 /* Bases of da850/da830 McASP0 register banks */
21 /* Bases of da830 McASP1 register banks */
24 /* Bases of da830 McASP2 register banks */
/linux-4.4.14/arch/x86/kernel/cpu/mcheck/
H A Dmce_intel.c24 * Also supports reliable discovery of shared banks.
33 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
34 * disables CMCI on all banks owned by the cpu and clears this bitfield. At
36 * taking ownership of some of the shared MCA banks that were previously
73 static int cmci_supported(int *banks) cmci_supported() argument
90 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); cmci_supported()
257 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
259 * banks.
261 static void cmci_discover(int banks) cmci_discover() argument
269 for (i = 0; i < banks; i++) { cmci_discover()
276 /* Skip banks in firmware first mode */ cmci_discover()
311 * We are able to set thresholds for some banks that cmci_discover()
326 "bios_cmci_threshold: Some banks do not have valid thresholds set\n"); cmci_discover()
334 * all the CMCI owned banks.
339 int banks; cmci_recheck() local
341 if (!mce_available(raw_cpu_ptr(&cpu_info)) || !cmci_supported(&banks)) cmci_recheck()
363 * Disable CMCI on this CPU for all banks it owns when it goes down.
364 * This allows other CPUs to claim the banks on rediscovery.
370 int banks; cmci_clear() local
372 if (!cmci_supported(&banks)) cmci_clear()
375 for (i = 0; i < banks; i++) cmci_clear()
382 int banks; cmci_rediscover_work_func() local
384 /* Recheck banks in case CPUs don't all have the same */ cmci_rediscover_work_func()
385 if (cmci_supported(&banks)) cmci_rediscover_work_func()
386 cmci_discover(banks); cmci_rediscover_work_func()
392 int banks; cmci_rediscover() local
394 if (!cmci_supported(&banks)) cmci_rediscover()
405 int banks; cmci_reenable() local
406 if (cmci_supported(&banks)) cmci_reenable()
407 cmci_discover(banks); cmci_reenable()
412 int banks; cmci_disable_bank() local
415 if (!cmci_supported(&banks)) cmci_disable_bank()
425 int banks; intel_init_cmci() local
427 if (!cmci_supported(&banks)) intel_init_cmci()
431 cmci_discover(banks); intel_init_cmci()
435 * check for the banks later for CPU #0 just to make sure intel_init_cmci()
H A Dmce.c97 * MCA banks polled by the period polling timer for corrected events.
98 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
105 * MCA banks controlled through firmware first for corrected errors.
106 * This is a global list of banks for which we won't enable CMCI and we
107 * won't poll. Firmware controls these banks and is responsible for
579 for (i = 0; i < mca_cfg.banks; i++) { machine_check_poll()
661 for (i = 0; i < mca_cfg.banks; i++) { mce_no_way_out()
844 * This way when there are any shared banks it will be mce_start()
955 for (i = 0; i < mca_cfg.banks; i++) { mce_clear_state()
1017 if (!cfg->banks) do_machine_check()
1045 * Go through all the banks in exclusion of the other CPUs. do_machine_check()
1046 * This way we don't report duplicated events on shared banks do_machine_check()
1053 for (i = 0; i < cfg->banks; i++) { do_machine_check()
1358 u8 num_banks = mca_cfg.banks; __mcheck_cpu_mce_banks_init()
1384 if (!mca_cfg.banks) __mcheck_cpu_cap_init()
1385 pr_info("CPU supports %d MCE banks\n", b); __mcheck_cpu_cap_init()
1388 pr_warn("Using only %u machine check banks out of %u\n", __mcheck_cpu_cap_init()
1394 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); __mcheck_cpu_cap_init()
1395 mca_cfg.banks = b; __mcheck_cpu_cap_init()
1436 for (i = 0; i < mca_cfg.banks; i++) { __mcheck_cpu_init_generic()
1486 if (c->x86 == 15 && cfg->banks > 4) { __mcheck_cpu_apply_quirks()
1505 if (c->x86 == 6 && cfg->banks > 0) __mcheck_cpu_apply_quirks()
1516 * Turn off MC4_MISC thresholding banks on those models since __mcheck_cpu_apply_quirks()
1557 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) __mcheck_cpu_apply_quirks()
1982 if (bank >= mca_cfg.banks) { mce_disable_bank()
2064 for (i = 0; i < mca_cfg.banks; i++) { mce_disable_error_reporting()
2331 for (j = 0; j < mca_cfg.banks; j++) { mce_device_create()
2363 for (i = 0; i < mca_cfg.banks; i++) mce_device_remove()
2395 for (i = 0; i < mca_cfg.banks; i++) { mce_reenable_cpu()
2447 for (i = 0; i < mca_cfg.banks; i++) { mce_init_banks()
H A Dmce_amd.c62 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
259 for (bank = 0; bank < mca_cfg.banks; ++bank) { mce_amd_feature_init()
364 for (bank = 0; bank < mca_cfg.banks; ++bank) { amd_deferred_error_interrupt()
393 for (bank = 0; bank < mca_cfg.banks; ++bank) { amd_threshold_interrupt()
575 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) allocate_threshold_blocks()
740 /* create dir/files for all valid threshold banks */ threshold_create_device()
747 bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, threshold_create_device()
754 for (bank = 0; bank < mca_cfg.banks; ++bank) { threshold_create_device()
836 for (bank = 0; bank < mca_cfg.banks; ++bank) { threshold_remove_device()
/linux-4.4.14/arch/arm/mach-omap2/
H A Dpowerdomains7xx_data.c40 .banks = 4,
80 .banks = 2,
99 .banks = 1,
116 .banks = 2,
134 .banks = 1,
150 .banks = 1,
165 .banks = 5,
198 .banks = 1,
214 .banks = 1,
230 .banks = 1,
247 .banks = 2,
265 .banks = 3,
285 .banks = 1,
301 .banks = 1,
316 .banks = 3,
336 .banks = 3,
356 .banks = 1,
372 .banks = 1,
388 .banks = 1,
404 .banks = 1,
H A Dpowerdomains2xxx_data.c34 .banks = 1,
49 .banks = 1,
64 .banks = 3,
90 .banks = 1,
H A Dpowerdomains43xx_data.c26 .banks = 1,
40 .banks = 3,
68 .banks = 1,
98 .banks = 4,
H A Dpowerdomains44xx_data.c41 .banks = 5,
66 .banks = 1,
84 .banks = 2,
104 .banks = 1,
122 .banks = 3,
143 .banks = 1,
160 .banks = 1,
177 .banks = 1,
193 .banks = 1,
210 .banks = 3,
231 .banks = 4,
254 .banks = 1,
272 .banks = 1,
290 .banks = 2,
H A Dpowerdomains54xx_data.c39 .banks = 5,
65 .banks = 2,
94 .banks = 1,
112 .banks = 1,
129 .banks = 1,
145 .banks = 1,
162 .banks = 2,
191 .banks = 3,
212 .banks = 1,
230 .banks = 2,
249 .banks = 1,
266 .banks = 1,
282 .banks = 4,
H A Dpowerdomains3xxx_data.c40 .banks = 4,
62 .banks = 1,
78 .banks = 1,
103 .banks = 2,
125 .banks = 2,
142 .banks = 2,
159 .banks = 1,
174 .banks = 1,
195 .banks = 1,
210 .banks = 1,
225 .banks = 1,
240 .banks = 1,
255 .banks = 1,
299 .banks = 1,
H A Dpowerdomains33xx_data.c33 .banks = 1,
84 .banks = 3,
127 .banks = 3,
H A Dpowerdomains2xxx_3xxx_data.c50 .banks = 1,
H A Dpowerdomain.c128 for (i = 0; i < pwrdm->banks; i++) _pwrdm_register()
151 for (i = 0; i < pwrdm->banks; i++) { _update_logic_membank_counters()
486 * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
489 * Return the number of controllable memory banks in powerdomain @pwrdm,
497 return pwrdm->banks; pwrdm_get_mem_bank_count()
654 if (pwrdm->banks < (bank + 1)) pwrdm_set_mem_onst()
692 if (pwrdm->banks < (bank + 1)) pwrdm_set_mem_retst()
788 if (pwrdm->banks < (bank + 1)) pwrdm_read_mem_pwrst()
818 if (pwrdm->banks < (bank + 1)) pwrdm_read_prev_mem_pwrst()
847 if (pwrdm->banks < (bank + 1)) pwrdm_read_mem_retst()
1154 for (i = 0; i < pwrdm->banks; i++) pwrdm_get_context_loss_count()
1198 for (i = 0; i < pwrdm->banks; i++) pwrdm_can_ever_lose_context()
1203 for (i = 0; i < pwrdm->banks; i++) pwrdm_can_ever_lose_context()
H A Dpowerdomain.h61 * Number of memory banks that are power-controllable. On OMAP4430, the
88 * @banks: Number of software-controllable memory banks in this powerdomain
122 const u8 banks; member in struct:powerdomain
H A Dpm-debug.c113 for (i = 0; i < pwrdm->banks; i++) pwrdm_dbg_show_counter()
H A Dpm24xx.c203 * Set CORE powerdomain memory banks to retain their contents prcm_setup_regs()
/linux-4.4.14/drivers/memory/
H A Dfsl_ifc.c53 * This function walks IFC banks comparing "Base address" field of the CSPR
65 for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) { fsl_ifc_find()
211 * resources for the NAND banks themselves are allocated
217 int version, banks; fsl_ifc_ctrl_probe() local
237 banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; fsl_ifc_ctrl_probe()
238 dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", fsl_ifc_ctrl_probe()
239 version >> 24, (version >> 16) & 0xf, banks); fsl_ifc_ctrl_probe()
242 fsl_ifc_ctrl_dev->banks = banks; fsl_ifc_ctrl_probe()
254 banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; fsl_ifc_ctrl_probe()
255 dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", fsl_ifc_ctrl_probe()
256 version >> 24, (version >> 16) & 0xf, banks); fsl_ifc_ctrl_probe()
259 fsl_ifc_ctrl_dev->banks = banks; fsl_ifc_ctrl_probe()
H A Djz4780-nemc.c57 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
58 * @dev: device to count banks for, must be a child of the NEMC.
60 * Return: The number of unique NEMC banks referred to by the specified NEMC
/linux-4.4.14/arch/arm/mach-sa1100/include/mach/
H A Dmemory.h13 * Because of the wide memory address space between physical RAM banks on the
18 * The sparsemem banks are matched with the physical memory bank addresses
/linux-4.4.14/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h96 * @nr_banks: count of banks being part of the mux
97 * @banks: array of banks being part of the mux
101 struct samsung_pin_bank *banks[]; member in struct:exynos_muxed_weint_data
H A Dpinctrl-exynos.c458 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; exynos_irq_demux_eint16_31()
466 struct samsung_pin_bank *b = eintd->banks[i]; exynos_irq_demux_eint16_31()
575 muxed_data->banks[idx++] = bank; exynos_eint_wkup_init()
646 /* pin banks of s5pv210 pin-controller */
696 /* pin banks of exynos3250 pin-controller 0 */
707 /* pin banks of exynos3250 pin-controller 1 */
750 /* pin banks of exynos4210 pin-controller 0 */
770 /* pin banks of exynos4210 pin-controller 1 */
794 /* pin banks of exynos4210 pin-controller 2 */
826 /* pin banks of exynos4x12 pin-controller 0 */
843 /* pin banks of exynos4x12 pin-controller 1 */
870 /* pin banks of exynos4x12 pin-controller 2 */
875 /* pin banks of exynos4x12 pin-controller 3 */
921 /* pin banks of exynos4415 pin-controller 0 */
935 /* pin banks of exynos4415 pin-controller 1 */
960 /* pin banks of exynos4415 pin-controller 2 */
996 /* pin banks of exynos5250 pin-controller 0 */
1025 /* pin banks of exynos5250 pin-controller 1 */
1038 /* pin banks of exynos5250 pin-controller 2 */
1047 /* pin banks of exynos5250 pin-controller 3 */
1089 /* pin banks of exynos5260 pin-controller 0 */
1114 /* pin banks of exynos5260 pin-controller 1 */
1123 /* pin banks of exynos5260 pin-controller 2 */
1153 /* pin banks of exynos5420 pin-controller 0 */
1162 /* pin banks of exynos5420 pin-controller 1 */
1179 /* pin banks of exynos5420 pin-controller 2 */
1191 /* pin banks of exynos5420 pin-controller 3 */
1204 /* pin banks of exynos5420 pin-controller 4 */
1243 /* pin banks of exynos5433 pin-controller - ALIVE */
1251 /* pin banks of exynos5433 pin-controller - AUD */
1257 /* pin banks of exynos5433 pin-controller - CPIF */
1262 /* pin banks of exynos5433 pin-controller - eSE */
1267 /* pin banks of exynos5433 pin-controller - FINGER */
1272 /* pin banks of exynos5433 pin-controller - FSYS */
1282 /* pin banks of exynos5433 pin-controller - IMEM */
1287 /* pin banks of exynos5433 pin-controller - NFC */
1292 /* pin banks of exynos5433 pin-controller - PERIC */
1313 /* pin banks of exynos5433 pin-controller - TOUCH */
1396 /* pin banks of exynos7 pin-controller - ALIVE */
1404 /* pin banks of exynos7 pin-controller - BUS0 */
1423 /* pin banks of exynos7 pin-controller - NFC */
1428 /* pin banks of exynos7 pin-controller - TOUCH */
1433 /* pin banks of exynos7 pin-controller - FF */
1438 /* pin banks of exynos7 pin-controller - ESE */
1443 /* pin banks of exynos7 pin-controller - FSYS0 */
1448 /* pin banks of exynos7 pin-controller - FSYS1 */
1456 /* pin banks of exynos7 pin-controller - BUS1 */
H A Dpinctrl-samsung.h71 * Samsung GPIO controller groups all the available pins into banks. The pins
183 * @pin_banks: list of pin banks included in this controller.
184 * @nr_banks: number of pin banks.
H A Dpinctrl-samsung.c382 /* Some banks have two config registers */ samsung_pinmux_setup()
584 /* Some banks have two config registers */ samsung_gpio_set_direction()
1082 * Save data for all banks handled by this device.
1106 /* Some banks have two config registers */ samsung_pinctrl_suspend_dev()
1126 * Restore one of the banks that was saved during suspend.
1151 /* Some banks have two config registers */ samsung_pinctrl_resume_dev()
1174 * Save data for all banks across all devices.
1190 * Restore data for all banks across all devices.
H A Dpinctrl-s3c64xx.c204 * @pins: pin offsets inside of banks of particular EINT0 interrupts
431 /* Group 1 is used for two pin banks */ s3c64xx_eint_gpio_irq()
778 /* pin banks of s3c64xx pin-controller 0 */
/linux-4.4.14/arch/arm/include/asm/
H A Dsparsemem.h15 * Eg, if you have 2 banks of up to 64MB at 0x80000000, 0x84000000,
/linux-4.4.14/drivers/pinctrl/meson/
H A Dpinctrl-meson.h103 * @banks: set of banks belonging to the domain
104 * @num_banks: number of banks in the domain
108 struct meson_bank *banks; member in struct:meson_domain_data
125 * A domain represents a set of banks controlled by the same set of
H A Dpinctrl-meson.c15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
22 * registers different from the other banks.
41 * can be shared by more banks with different offsets.
44 * banks that control the IRQ functionality. This feature is not
82 if (pin >= domain->data->banks[i].first && meson_get_bank()
83 pin <= domain->data->banks[i].last) { meson_get_bank()
84 *bank = &domain->data->banks[i]; meson_get_bank()
H A Dpinctrl-meson8.c927 .name = "banks",
928 .banks = meson8_banks,
935 .banks = meson8_ao_banks,
H A Dpinctrl-meson8b.c875 .name = "banks",
876 .banks = meson8b_banks,
883 .banks = meson8b_ao_banks,
/linux-4.4.14/drivers/pinctrl/qcom/
H A Dpinctrl-ssbi-gpio.c316 u8 banks = 0; pm8xxx_pin_config_set() local
326 banks |= BIT(2); pm8xxx_pin_config_set()
328 banks |= BIT(3); pm8xxx_pin_config_set()
332 banks |= BIT(2); pm8xxx_pin_config_set()
334 banks |= BIT(3); pm8xxx_pin_config_set()
345 banks |= BIT(2); pm8xxx_pin_config_set()
347 banks |= BIT(3); pm8xxx_pin_config_set()
351 banks |= BIT(3); pm8xxx_pin_config_set()
355 banks |= BIT(0) | BIT(1); pm8xxx_pin_config_set()
360 banks |= BIT(0) | BIT(1); pm8xxx_pin_config_set()
364 banks |= BIT(0); pm8xxx_pin_config_set()
372 banks |= BIT(3); pm8xxx_pin_config_set()
376 banks |= BIT(1); pm8xxx_pin_config_set()
380 banks |= BIT(1); pm8xxx_pin_config_set()
390 if (banks & BIT(0)) { pm8xxx_pin_config_set()
396 if (banks & BIT(1)) { pm8xxx_pin_config_set()
403 if (banks & BIT(2)) { pm8xxx_pin_config_set()
408 if (banks & BIT(3)) { pm8xxx_pin_config_set()
414 if (banks & BIT(4)) { pm8xxx_pin_config_set()
419 if (banks & BIT(5)) { pm8xxx_pin_config_set()
/linux-4.4.14/arch/powerpc/sysdev/
H A Dfsl_msi.h48 struct list_head list; /* support multiple MSI banks */
H A Dfsl_lbc.c62 * This function walks LBC banks comparing "Base address" field of the BR
277 * resources for the NAND banks themselves are allocated
/linux-4.4.14/arch/mips/include/asm/mach-jz4740/
H A Djz4740_nand.h30 unsigned char banks[JZ_NAND_NUM_BANKS]; member in struct:jz_nand_platform_data
/linux-4.4.14/include/linux/
H A Djz4780-nemc.h21 * Number of NEMC banks. Note that there are actually 6, but they are numbered
H A DmISDNdsp.h33 int pcm_banks; /* number of IO banks of pcm bus */
H A Dof_gpio.h38 * OF GPIO chip for memory mapped banks
H A Dfsl_ifc.h33 * The actual number of banks implemented depends on the IFC version
34 * - IFC version 1.0 implements 4 banks.
35 * - IFC version 1.1 onward implements 8 banks.
840 int banks; member in struct:fsl_ifc_ctrl
/linux-4.4.14/drivers/mtd/nand/
H A Djz4740_nand.c67 unsigned char banks[JZ_NAND_NUM_BANKS]; member in struct:jz_nand
95 banknr = nand->banks[chipnr] - 1; jz_nand_select_chip()
461 /* We are going to autodetect NAND chips in the banks specified in the jz_nand_probe()
464 * always the case for external memory banks. And a fixed chip-to-bank jz_nand_probe()
466 * produced at different times have NAND chips in different banks. jz_nand_probe()
476 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1; jz_nand_probe()
485 * jz_nand_select_chip(), so nand->banks has to contain the jz_nand_probe()
488 nand->banks[chipnr] = bank; jz_nand_probe()
493 nand->banks[chipnr] = 0; jz_nand_probe()
528 unsigned char bank = nand->banks[chipnr]; jz_nand_probe()
552 unsigned char bank = nand->banks[i]; jz_nand_remove()
H A Dfsl_ifc_nand.c1048 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { fsl_ifc_nand_probe()
1053 if (bank >= fsl_ifc_ctrl_dev->banks) { fsl_ifc_nand_probe()
H A Ddenali.c313 * reset all the banks before get_onfi_nand_para()
456 * banks that the hardware supports.
H A Datmel_nand.c315 /* NFC only has two banks. Must be 0 or 1 */ nfc_set_sram_bank()
320 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */ nfc_set_sram_bank()
/linux-4.4.14/drivers/crypto/qat/qat_dh895xcc/
H A Dadf_isr.c172 /* Request msix irq for all banks unless SR-IOV enabled */ adf_request_irqs()
175 struct adf_etr_bank_data *bank = &etr_data->banks[i]; adf_request_irqs()
222 free_irq(msixe[i].vector, &etr_data->banks[i]); adf_free_irqs()
286 tasklet_init(&priv_data->banks[i].resp_handler, adf_setup_bh()
288 (unsigned long)&priv_data->banks[i]); adf_setup_bh()
299 tasklet_disable(&priv_data->banks[i].resp_handler); adf_cleanup_bh()
300 tasklet_kill(&priv_data->banks[i].resp_handler); adf_cleanup_bh()
H A Dadf_drv.c126 int banks = GET_MAX_BANKS(accel_dev); adf_dev_configure() local
127 int instances = min(cpus, banks); adf_dev_configure()
/linux-4.4.14/arch/arm/kernel/
H A Dtcm.c110 static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, setup_tcm_bank() argument
123 if (banks > 1) setup_tcm_bank()
293 /* Values greater than 2 for D/ITCM banks are "reserved" */ tcm_init()
314 * This means that the DTCM sizes were 0 or the DTCM banks tcm_init()
333 "DTCM banks present in CPU\n", dtcm_code_sz); tcm_init()
352 * This means that the ITCM sizes were 0 or the ITCM banks tcm_init()
371 "ITCM banks present in CPU\n", itcm_code_sz); tcm_init()
/linux-4.4.14/drivers/crypto/qat/qat_dh895xccvf/
H A Dadf_isr.c178 struct adf_etr_bank_data *bank = &etr_data->banks[0]; adf_isr()
216 tasklet_init(&priv_data->banks[0].resp_handler, adf_response_handler, adf_setup_bh()
217 (unsigned long)priv_data->banks); adf_setup_bh()
225 tasklet_disable(&priv_data->banks[0].resp_handler); adf_cleanup_bh()
226 tasklet_kill(&priv_data->banks[0].resp_handler); adf_cleanup_bh()
/linux-4.4.14/arch/x86/include/asm/
H A Dmce.h87 /* Software defined banks */
117 u8 banks; member in struct:mca_config
141 * banks. Also, to accommodate the new banks and registers, the MCA
186 * Maximum banks number. enable_p5_mce()
/linux-4.4.14/drivers/gpio/
H A Dgpio-bcm-kona.c70 struct bcm_kona_gpio_bank *banks; member in struct:bcm_kona_gpio
587 dev_err(dev, "Couldn't determine # GPIO banks\n"); bcm_kona_gpio_probe()
591 dev_err(dev, "Too many GPIO banks configured (max=%d)\n", bcm_kona_gpio_probe()
595 kona_gpio->banks = devm_kzalloc(dev, bcm_kona_gpio_probe()
597 sizeof(*kona_gpio->banks), GFP_KERNEL); bcm_kona_gpio_probe()
598 if (!kona_gpio->banks) bcm_kona_gpio_probe()
623 bank = &kona_gpio->banks[i]; bcm_kona_gpio_probe()
644 bank = &kona_gpio->banks[i]; bcm_kona_gpio_probe()
H A Dgpio-zynq.c25 /* Maximum banks */
119 * @max_bank: maximum number of gpio banks
518 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
660 * all the banks of the device. It will also set up interrupts for the gpio
662 * Note: Interrupts are disabled for all the banks during initialization.
730 /* disable interrupts for all banks */ zynq_gpio_probe()
H A Dgpio-brcmstb.c238 /* Each UPG GIO block has one IRQ for all banks */ brcmstb_gpio_irq_handler()
271 /* Make sure that the number of banks matches up between properties */ brcmstb_gpio_sanity_check_banks()
280 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", brcmstb_gpio_sanity_check_banks()
525 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n", brcmstb_gpio_probe()
H A Dgpio-davinci.c217 * The gpio banks conceptually expose a segmented bitmap, davinci_gpio_probe()
284 * All those INTC hookups (direct, plus several IRQ banks) can also
571 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we davinci_gpio_irq_setup()
H A Dgpio-msic.c67 * Both the high and low voltage gpios are divided in two banks.
H A Dgpio-xilinx.c43 * @mmchip: OF GPIO chip for memory mapped banks
H A Dgpio-pxa.c32 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
H A Dgpio-tz1090.c582 /* Look for banks */ tz1090_gpio_probe()
H A Dgpio-samsung.c478 * The samsung_gpiolib_4bit routines are to control the gpio banks where
768 /* skip banks not present on SoC */ s3c24xx_gpiolib_add_chips()
H A Dgpio-mcp23s08.c38 * with either 16 bit registers or with two adjacent 8 bit banks.
/linux-4.4.14/drivers/pinctrl/vt8500/
H A Dpinctrl-wmt.h65 const struct wmt_pinctrl_bank_registers *banks; member in struct:wmt_pinctrl_data
H A Dpinctrl-wmt.c98 u32 reg_en = data->banks[bank].reg_en; wmt_set_pinmux()
99 u32 reg_dir = data->banks[bank].reg_dir; wmt_set_pinmux()
435 u32 reg_pull_en = data->banks[bank].reg_pull_en; wmt_pinconf_set()
436 u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg; wmt_pinconf_set()
494 u32 reg_dir = data->banks[bank].reg_dir; wmt_gpio_get_direction()
509 u32 reg_data_in = data->banks[bank].reg_data_in; wmt_gpio_get_value()
525 u32 reg_data_out = data->banks[bank].reg_data_out; wmt_gpio_set_value()
H A Dpinctrl-wm8650.c30 * Do not reorder these banks as it will change the pin numbering
335 data->banks = wm8650_banks; wm8650_pinctrl_probe()
H A Dpinctrl-vt8500.c30 * Do not reorder these banks as it will change the pin numbering
466 data->banks = vt8500_banks; vt8500_pinctrl_probe()
H A Dpinctrl-wm8750.c30 * Do not reorder these banks as it will change the pin numbering
374 data->banks = wm8750_banks; wm8750_pinctrl_probe()
H A Dpinctrl-wm8850.c30 * Do not reorder these banks as it will change the pin numbering
353 data->banks = wm8850_banks; wm8850_pinctrl_probe()
H A Dpinctrl-wm8505.c30 * Do not reorder these banks as it will change the pin numbering
497 data->banks = wm8505_banks; wm8505_pinctrl_probe()
/linux-4.4.14/drivers/clk/tegra/
H A Dclk.c197 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) tegra_clk_init() argument
201 if (WARN_ON(banks > ARRAY_SIZE(periph_regs))) tegra_clk_init()
204 periph_clk_enb_refcnt = kzalloc(32 * banks * tegra_clk_init()
209 periph_banks = banks; tegra_clk_init()
H A Dclk-tegra124.c33 * banks present in the Tegra124/132 CAR IP block. The banks are
/linux-4.4.14/arch/sparc/prom/
H A Dprintf.c9 * and yet people do. Anton's banking code was outputting banks
/linux-4.4.14/arch/x86/boot/
H A Dvesa.h49 u8 banks; /* 26 */ member in struct:vesa_mode_info
/linux-4.4.14/arch/x86/kernel/acpi/
H A Dapei.c35 * We expect HEST to provide a list of MC banks that report errors arch_apei_enable_cmcff()
/linux-4.4.14/include/linux/spi/
H A Dmcp23s08.h34 * those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
/linux-4.4.14/arch/mips/include/asm/sn/
H A Dfru.h14 #define MAX_DIMMS 8 /* max # of dimm banks */
/linux-4.4.14/arch/mips/bcm63xx/
H A Dcpu.c258 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; detect_memory_size() local
274 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; detect_memory_size()
282 banks = 2; detect_memory_size()
291 return 1 << (cols + rows + (is_32bits + 1) + banks); detect_memory_size()
/linux-4.4.14/sound/pci/au88x0/
H A Dau88x0_wt.h11 /* WT channels are grouped in banks. Each bank has 0x20 channels. */
/linux-4.4.14/drivers/crypto/qat/qat_common/
H A Dadf_transport.c272 bank = &transport_data->banks[bank_num]; adf_create_ring()
487 etr_data->banks = kzalloc_node(size, GFP_KERNEL, adf_init_etr_data()
489 if (!etr_data->banks) { adf_init_etr_data()
509 ret = adf_init_bank(accel_dev, &etr_data->banks[i], i, adf_init_etr_data()
520 kfree(etr_data->banks); adf_init_etr_data()
553 cleanup_bank(&etr_data->banks[i]); adf_cleanup_etr_handles()
573 kfree(etr_data->banks); adf_cleanup_etr_data()
H A Dadf_hw_arbiter.c91 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; adf_init_arb()
150 csr = accel_dev->transport->banks[0].csr_addr; adf_exit_arb()
H A Dadf_transport_internal.h90 struct adf_etr_bank_data *banks; member in struct:adf_etr_data
/linux-4.4.14/drivers/i2c/
H A Di2c-stub.c83 /* For chips with banks, extra registers are allocated dynamically */
222 * We ignore banks here, because banked chips don't use I2C stub_xfer()
251 * We ignore banks here, because chips typically don't use both stub_xfer()
252 * banks and SMBus block transfers stub_xfer()
345 pr_debug("i2c-stub: Allocated %u banks of %u words each (registers 0x%02x to 0x%02x)\n", i2c_stub_allocate_banks()
/linux-4.4.14/arch/mips/sgi-ip27/
H A Dip27-memory.c269 klmembnk_t *banks; slot_psize_compute() local
279 banks = (klmembnk_t *) find_first_component(brd, KLSTRUCT_MEMBNK); slot_psize_compute()
280 if (!banks) slot_psize_compute()
284 size = (unsigned long)banks->membnk_bnksz[slot/4]; slot_psize_compute()
286 /* hack for 128 dimm banks */ slot_psize_compute()
/linux-4.4.14/drivers/nvmem/
H A Dmxs-ocotp.c87 /* open OCOTP banks for read */ mxs_ocotp_read()
111 /* close banks for power saving */ mxs_ocotp_read()
/linux-4.4.14/arch/blackfin/kernel/cplb-nompu/
H A Dcplbinit.c153 /* ASYNC banks. */ generate_cplb_tables_all()
192 /* ASYNC banks. */ generate_cplb_tables_all()
/linux-4.4.14/include/video/
H A Duvesafb.h50 u8 banks; member in struct:vbe_mode_ib
/linux-4.4.14/arch/arm/plat-orion/
H A Dpcie.c120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
151 * Setup windows for DDR banks. Count total DDR size on the fly. orion_pcie_setup_wins()
174 * Setup BAR[1] to all DRAM banks. orion_pcie_setup_wins()
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-st.c329 struct st_gpio_bank *banks; member in struct:st_pinctrl
1193 * So each register is shared across 4 banks. st_parse_syscfgs()
1197 struct st_pio_control *pc = &info->banks[bank].pc; st_parse_syscfgs()
1477 __gpio_irq_handler(&info->banks[n]); st_gpio_irqmux_handler()
1507 struct st_gpio_bank *bank = &info->banks[bank_nr]; st_gpiolib_register_bank()
1547 * gpio banks. This reduces number of overall interrupts numbers st_gpiolib_register_bank()
1548 * required. All these banks belong to a single pincontroller. st_gpiolib_register_bank()
1631 info->banks = devm_kzalloc(&pdev->dev, st_pctl_probe_dt()
1632 info->nbanks * sizeof(*info->banks), GFP_KERNEL); st_pctl_probe_dt()
1634 if (!info->functions || !info->groups || !info->banks) st_pctl_probe_dt()
1675 k = info->banks[bank].range.pin_base; for_each_child_of_node()
1676 bank_name = info->banks[bank].range.name; for_each_child_of_node()
1736 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); st_pctl_probe()
H A Dpinctrl-adi2.c107 * banks can be mapped into one Pin interrupt controller.
118 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
122 * multiple GPIO banks.
152 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
H A Dpinctrl-at91-pio4.c36 * framework groups, Atmel PIO groups will be called banks, line is kept to
862 * The number of banks can be different from a SoC to another one.
863 * We can have up to 16 banks.
H A Dpinctrl-at91.c71 * that are even in the same banks. It is also dependent on VCC.
1584 * to process multiple banks (like ID_PIOCDE on sam9263). gpio_irq_handler()
1653 /* we can only have 2 banks before */ at91_gpio_of_irq_setup()
H A Dpinctrl-falcon.c439 /* load and remap the pad resources of the different banks */ pinctrl_falcon_probe()
H A Dpinctrl-xway.c27 /* we have 3 1/2 banks of 16 bit each */
/linux-4.4.14/drivers/mtd/maps/
H A Dsc520cdp.c21 * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
50 ** choose more useful addresses for the FLASH banks by reprogramming the
266 /* Combine the two flash banks into a single MTD device & register it: */ init_sc520cdp()
/linux-4.4.14/arch/arm/plat-samsung/
H A Dpm-gpio.c103 * Restore one of the GPIO banks that was saved during suspend. This is
324 * samsung_pm_save_gpios() - Save the state of the GPIO banks.
326 * For all the GPIO banks, save the state of each one ready for going
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Ddt2817.c25 A very simple digital I/O card. Four banks of 8 lines, each bank
H A Dcb_pcimdda.c29 configurable in banks of 8 and 4, etc.). This board does not support commands.
H A Dni_tiocmd.c43 Support use of both banks X and Y
H A Dni_tio.c43 Support use of both banks X and Y
/linux-4.4.14/arch/blackfin/mach-bf538/
H A Dext-gpio.c79 /* We don't set the irq fields as these banks cannot generate interrupts */
/linux-4.4.14/arch/mips/include/asm/mach-rc32434/
H A Dddr.h51 /* DDR banks masks */
/linux-4.4.14/arch/arm/mach-realview/include/mach/
H A Dboard-pb1176.h33 #define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
H A Dplatform.h190 #define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
/linux-4.4.14/drivers/irqchip/
H A Dirq-bcm2835.c35 * their respective banks' enable/disable registers. Doing so in the bank 0
39 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
H A Dirq-metag-ext.c29 * @nr_banks: Number of interrupt banks
30 * @domain: IRQ domain for all banks of external IRQs
824 /* Get number of banks */ init_external_IRQ()
825 ret = of_property_read_u32(node, "num-banks", &val); init_external_IRQ()
827 pr_err("meta-intc: No num-banks property found\n"); init_external_IRQ()
831 pr_err("meta-intc: num-banks (%u) out of range\n", val); init_external_IRQ()
H A Dirq-renesas-intc-irqpin.c425 /* get hold of register banks */ intc_irqpin_probe()
/linux-4.4.14/drivers/net/ethernet/smsc/
H A Dsmc9194.h45 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
49 . The banks are configured so that for most purposes, bank 2 is all
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A Diotiming-s3c2412.c139 * Calculate the timing information for all the banks that are
239 /* look through all banks to see what is currently set. */ s3c2412_iotiming_get()
H A Diotiming-s3c2410.c357 * Calculate the new values for the banks in @iot based on the new
427 * through all the IO banks, reading the state and then updating @iot
445 /* look through all banks to see what is currently set. */ s3c2410_iotiming_get()
/linux-4.4.14/sound/oss/
H A Dopl3_hw.h82 * Offsets to the register banks for operators. To get the
121 * Offsets to the register banks for voices. Just add to the
/linux-4.4.14/drivers/video/fbdev/
H A Dcontrolfb.h69 struct preg vram_attr; /* enable vram banks */
H A Dmacfb.c343 * apparently, there are two different banks of 512K RAM
H A Dcontrolfb.c606 /* Work out which banks of VRAM we have installed. */
/linux-4.4.14/drivers/iommu/
H A Dmsm_iommu.h48 * ncb Number of context banks present on this IOMMU HW instance
H A Dmsm_iommu_dev.c222 pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", msm_iommu_probe()
H A Darm-smmu.c53 /* Maximum number of context banks per SMMU */
1474 /* Make sure all context banks are disabled and clear CB_FSR */ arm_smmu_device_reset()
1637 dev_err(smmu->dev, "impossible number of S2 context banks!\n"); arm_smmu_device_cfg_probe()
1640 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", arm_smmu_device_cfg_probe()
H A Damd_iommu_types.h561 /* The maximum PC banks and counters/bank (PCSup=1) */
H A Dipmmu-vmsa.c790 * The IPMMU has two register banks, for secure and non-secure modes. ipmmu_probe()
/linux-4.4.14/drivers/media/rc/
H A Dite-cir.h393 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
394 * selectable by a single bank-select bit that's mapped onto both banks. The
397 * reserved high-order bit are placed at the same offset in both banks in
403 /* mapped onto both banks */
H A Dwinbond-cir.c81 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
160 /* Valid banks for the SP3 UART */
/linux-4.4.14/drivers/misc/eeprom/
H A Dmax6875.c8 * The MAX6875 has a bank of registers and two banks of EEPROM.
/linux-4.4.14/arch/alpha/kernel/
H A Dsys_ruffian.c186 since Ruffian only uses three banks. */ ruffian_get_bank_size()
/linux-4.4.14/arch/mips/include/asm/octeon/
H A Docteon-feature.h59 /* Octeon has a LED controller for banks of external LEDs */
/linux-4.4.14/arch/sh/drivers/
H A Dheartbeat.c2 * Generic heartbeat driver for regular LED banks
/linux-4.4.14/arch/mips/alchemy/devboards/
H A Dplatform.c202 * to swap the physical locations of the 2 NOR flash banks. db1x_register_norflash()
/linux-4.4.14/arch/powerpc/boot/
H A D4xx.c242 /* get collomn size and banks */ ibm4xx_denali_fixup_memsize()
251 bank = 8; /* 8 banks */ ibm4xx_denali_fixup_memsize()
253 bank = 4; /* 4 banks */ ibm4xx_denali_fixup_memsize()
306 * banks into the OPB address space */ ibm4xx_fixup_ebc_ranges()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dgpio-core.h67 * CPU cores trying to get one lock for different GPIO banks, where each
/linux-4.4.14/arch/arm/mach-pxa/
H A Dsleep.S20 #define MDREFR_KDIV 0x200a4000 // all banks
H A Dlubbock.c479 /* Compensate for the nROMBT switch which swaps the flash banks */ lubbock_init()
H A Dhx4700.c224 /* ASIC3 GPIO banks A and B along with some of C and D
H A Dmainstone.c522 /* Compensate for SW7 which swaps the flash banks */ mainstone_init()
/linux-4.4.14/arch/arm/mach-s3c64xx/include/mach/
H A Dregs-gpio.h14 /* Base addresses for each of the banks */
/linux-4.4.14/drivers/edac/
H A Dr82600_edac.c35 * supports up to four banks of memory. The four banks can support a mix of
H A Di7core_edac.c430 static const int banks[] = { 4, 8, 16, -EINVAL }; numbank() local
432 return banks[bank & 0x3]; numbank()
594 u32 banks, ranks, rows, cols; get_dimm_config() local
602 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); get_dimm_config()
607 /* DDR3 has 8 I/O banks */ get_dimm_config()
608 size = (rows * cols * banks * ranks) >> (20 - 3); get_dimm_config()
613 banks, ranks, rows, cols); get_dimm_config()
619 switch (banks) { get_dimm_config()
H A Di82975x_edac.c164 * 00 => 4 banks
165 * 01 => 8 banks
H A Dppc4xx_edac.c43 * - Two (2) memory banks/ranks.
70 * - Four (4) memory banks/ranks.
882 * the csrows (i.e. banks/ranks) are being initialized.
928 * row/bank/rank and skip disabled banks. ppc4xx_edac_init_csrows()
H A Dsb_edac.c932 unsigned i, j, banks, ranks, rows, cols, npages; get_dimm_config() local
987 banks = 16; get_dimm_config()
989 banks = 8; get_dimm_config()
1009 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); get_dimm_config()
1015 banks, ranks, rows, cols); get_dimm_config()
/linux-4.4.14/arch/unicore32/mm/
H A Dinit.c149 * memory banks over to bootmem. uc32_bootmem_init()
353 * The banks are sorted previously in bootmem_init(). free_unused_memmap()
H A Dmmu.c398 /* Map all the lowmem memory banks. */ for_each_memblock()
/linux-4.4.14/include/sound/
H A Dopl3.h108 * Offsets to the register banks for operators. To get the
148 * Offsets to the register banks for voices. Just add to the
H A Dgus.h311 unsigned int rom_banks; /* GUS's ROM banks */
/linux-4.4.14/arch/mips/include/asm/sgi/
H A Dmc.h220 /* Base location of the two ram banks found in IP2[0268] machines. */
224 /* Maximum size of the above banks are per machine. */
/linux-4.4.14/arch/blackfin/kernel/
H A Dprocess.c260 * We can't read EBIU banks that aren't enabled or we end up hanging
262 * that cross async banks too.
H A Dsetup.c962 /* Initialize Async memory banks */
1385 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", show_cpuinfo()
1391 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", show_cpuinfo()
H A Dtrace.c239 /* Data banks will never have instructions */ get_instruction()
/linux-4.4.14/arch/arm/mach-mxs/
H A Dmach-mxs.c123 /* open OCOTP banks for read */ mxs_get_ocotp()
141 /* close banks for power saving */ mxs_get_ocotp()
/linux-4.4.14/sound/isa/gus/
H A Dgus_mem.c300 snd_iprintf(buffer, "8-bit banks : \n "); snd_gf1_mem_info_read()
304 "16-bit banks : \n "); snd_gf1_mem_info_read()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c603 int colbits, rowbitsa, rowbitsb, banks; nv50_fb_vram_rblock() local
616 banks = 1 << (((r4 & 0x03000000) >> 24) + 2); nv50_fb_vram_rblock()
618 rowsize = ram->parts * banks * (1 << colbits) * 8; nv50_fb_vram_rblock()
/linux-4.4.14/arch/arm/mach-orion5x/
H A Dpci.c34 * access to DDR banks.
421 * Setup windows for DDR banks. orion5x_setup_pci_wins()
/linux-4.4.14/drivers/acpi/apei/
H A Dhest.c122 * along with a set of MC banks which work in FF mode.
/linux-4.4.14/arch/mips/jz4740/
H A Dboard-qi_lb60.c143 .banks = { 1 },
/linux-4.4.14/arch/mips/ath25/
H A Dar5312.c215 /* Disable other flash banks */ ar5312_flash_init()
H A Dar5312_regs.h177 * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
/linux-4.4.14/arch/mips/sgi-ip22/
H A Dip22-mc.c85 /* Figure out how are memory banks mapped into spaces */ probe_memory()
/linux-4.4.14/arch/blackfin/mach-bf537/boards/
H A Ddnp5370.c114 /* 4 MB NOR flash attached to async memory banks 0-2,
/linux-4.4.14/arch/arm/mach-omap1/
H A Dirq.c241 pr_info("Total of %lu interrupts in %i interrupt banks\n", omap1_init_irq()
/linux-4.4.14/arch/arm/mach-realview/
H A Dcore.c393 * Setup the memory banks.
/linux-4.4.14/sound/drivers/opl4/
H A Dopl4_local.h58 * Offsets to the register banks for voices. To get the
/linux-4.4.14/drivers/pinctrl/bcm/
H A Dpinctrl-cygnus-gpio.c76 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
154 /* go through the entire GPIO banks and handle all interrupts */ cygnus_gpio_irq_handler()
/linux-4.4.14/arch/xtensa/variants/de212/include/variant/
H A Dcore.h266 #define XCHAL_DCACHE_BANKS 1 /* number of banks */
301 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */
/linux-4.4.14/arch/mips/include/asm/sibyte/
H A Dbcm1480_regs.h165 #define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8))
/linux-4.4.14/arch/mips/include/asm/sn/sn0/
H A Dhubmd.h95 #define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
97 #define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
/linux-4.4.14/drivers/staging/vme/devices/
H A Dvme_pio2_core.c257 * configuration of the banks. pio2_probe()
/linux-4.4.14/drivers/pinctrl/sh-pfc/
H A Dsh_pfc.h202 * GP port style (32 ports banks)
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dperf_event_amd_iommu.c462 pr_info("perf: amd_iommu: Detected. (%d banks, %d counters/bank)\n", _init_perf_amd_iommu()
/linux-4.4.14/arch/x86/ras/
H A Dmce_amd_inj.c362 "\t banks in a processor varies and is family/model-specific, therefore, the\n"
/linux-4.4.14/arch/xtensa/mm/
H A Dinit.c64 * Move all memory banks starting at 'from' to a new place at 'to',
/linux-4.4.14/arch/arm/mach-versatile/include/mach/
H A Dplatform.h246 #define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
/linux-4.4.14/drivers/pci/host/
H A Dpci-mvebu.c200 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
228 /* Setup windows for DDR banks. Count total DDR size on the fly. */ mvebu_pcie_setup_wins()
249 /* Setup BAR[1] to all DRAM banks. */ mvebu_pcie_setup_wins()
/linux-4.4.14/drivers/pinctrl/sirf/
H A Dpinctrl-atlas7.c355 struct atlas7_gpio_bank banks[0]; member in struct:atlas7_gpio_chip
5387 u32 banks = ATLAS7_PINCTRL_REG_BANKS; atlas7_pinmux_probe() local
5404 for (idx = 0; idx < banks; idx++) { atlas7_pinmux_probe()
5429 for (idx = 0; idx < banks; idx++) { atlas7_pinmux_probe()
5584 return &a7gc->banks[GPIO_TO_BANK(gpio)]; atlas7_gpio_to_bank()
5755 bank = &a7gc->banks[idx]; atlas7_gpio_handle_irq()
5966 ret = of_property_read_u32(np, "gpio-banks", &nbank); atlas7_gpio_probe()
6039 bank = &a7gc->banks[idx]; atlas7_gpio_probe()
6088 bank = &a7gc->banks[idx]; atlas7_gpio_suspend_noirq()
6106 bank = &a7gc->banks[idx]; atlas7_gpio_resume_noirq()
/linux-4.4.14/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_main.c3025 u8 dw, rows, cols, banks, ranks; netxen_sysfs_read_dimm() local
3046 banks = NETXEN_DIMM_NUMBANKS(val); netxen_sysfs_read_dimm()
3092 if (!banks) { netxen_sysfs_read_dimm()
3093 netdev_err(netdev, "Invalid no of banks %x\n", banks); netxen_sysfs_read_dimm()
3129 dimm.size = ((1 << rows) * (1 << cols) * dw * banks * ranks) / 8; netxen_sysfs_read_dimm()
/linux-4.4.14/drivers/sbus/char/
H A Djsflash.c13 * TODO: Erase/program both banks of a 8MB SIMM.
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dni.c1074 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ cayman_gpu_init()
1079 case 0: /* four banks */ cayman_gpu_init()
1082 case 1: /* eight banks */ cayman_gpu_init()
1085 case 2: /* sixteen banks */ cayman_gpu_init()
H A Datombios_crtc.c1312 case 0: /* 4 banks */ dce4_crtc_do_set_base()
1315 case 1: /* 8 banks */ dce4_crtc_do_set_base()
1319 case 2: /* 16 banks */ dce4_crtc_do_set_base()
H A Devergreen.c3520 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ evergreen_gpu_init()
3525 case 0: /* four banks */ evergreen_gpu_init()
3528 case 1: /* eight banks */ evergreen_gpu_init()
3531 case 2: /* sixteen banks */ evergreen_gpu_init()
/linux-4.4.14/drivers/acpi/acpica/
H A Devgpeinit.c154 /* Check for GPE0/GPE1 overlap (if both banks exist) */ acpi_ev_gpe_initialize()
/linux-4.4.14/arch/x86/include/asm/xen/
H A Dinterface.h369 * MSR banks that are specified by offsets)
/linux-4.4.14/arch/powerpc/platforms/chrp/
H A Dsetup.c111 /* Memory banks */ chrp_show_cpuinfo()
/linux-4.4.14/arch/mips/mm/
H A Dcerr-sb1.c397 /* (hit all banks and ways) */ extract_ic()
/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/
H A DdefBF532.h574 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
575 #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
576 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
/linux-4.4.14/drivers/rtc/
H A Drtc-cmos.c155 /* Most newer x86 systems have two register banks, the first used
626 * won't address 128 bytes. Newer chips have multiple banks, cmos_do_probe()
/linux-4.4.14/drivers/mtd/devices/
H A Dpmc551.c18 * device, and various banks of DRAM/SDRAM onboard. This driver
31 * have available claims that all 4 of its DRAM banks have 64MiB
H A Dspear_smi.c58 #define BANK_EN (0xF << 0) /* enables all banks */
901 * initialization/allocation work. The routine looks for available memory banks,
/linux-4.4.14/drivers/hwmon/
H A Dasb100.c867 /* switch banks */ asb100_read_value()
912 /* switch banks */ asb100_write_value()
H A Dw83781d.c1284 /* switch banks */ w83781d_read_value_i2c()
1324 /* switch banks */ w83781d_write_value_i2c()
/linux-4.4.14/drivers/phy/
H A Dphy-miphy28lp.c571 * Enable the SSC on PLL for all banks miphy_sata_tune_ssc()
609 * Enable the SSC on PLL for all banks miphy_pcie_tune_ssc()
/linux-4.4.14/arch/x86/kvm/
H A Dx86.c2864 u64 *banks = vcpu->arch.mce_banks; kvm_vcpu_ioctl_x86_set_mce() local
2875 banks += 4 * mce->bank; kvm_vcpu_ioctl_x86_set_mce()
2880 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) kvm_vcpu_ioctl_x86_set_mce()
2888 if (banks[1] & MCI_STATUS_VAL) kvm_vcpu_ioctl_x86_set_mce()
2890 banks[2] = mce->addr; kvm_vcpu_ioctl_x86_set_mce()
2891 banks[3] = mce->misc; kvm_vcpu_ioctl_x86_set_mce()
2893 banks[1] = mce->status; kvm_vcpu_ioctl_x86_set_mce()
2895 } else if (!(banks[1] & MCI_STATUS_VAL) kvm_vcpu_ioctl_x86_set_mce()
2896 || !(banks[1] & MCI_STATUS_UC)) { kvm_vcpu_ioctl_x86_set_mce()
2897 if (banks[1] & MCI_STATUS_VAL) kvm_vcpu_ioctl_x86_set_mce()
2899 banks[2] = mce->addr; kvm_vcpu_ioctl_x86_set_mce()
2900 banks[3] = mce->misc; kvm_vcpu_ioctl_x86_set_mce()
2901 banks[1] = mce->status; kvm_vcpu_ioctl_x86_set_mce()
2903 banks[1] |= MCI_STATUS_OVER; kvm_vcpu_ioctl_x86_set_mce()
/linux-4.4.14/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_common.h288 * @alloc_ctx: videobuf2 allocator contexts for two memory banks
/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h1115 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1116 #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1117 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
/linux-4.4.14/arch/sparc/kernel/
H A Dchmc.c517 /* Given PHYS_ADDR, search memory controller banks for a match. */ chmc_find_bank()
/linux-4.4.14/arch/arm/mm/
H A Dinit.c370 * The banks are sorted previously in bootmem_init(). free_unused_memmap()
/linux-4.4.14/arch/arm64/mm/
H A Dmmu.c368 /* map all the memory banks */ for_each_memblock()
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dpxa168_eth.c554 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB init_hash_table()
555 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support init_hash_table()
/linux-4.4.14/drivers/usb/gadget/udc/
H A Datmel_usba_udc.c1980 ret = of_property_read_u32(pp, "atmel,nb-banks", &val); atmel_udc_of_init()
1982 dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret); atmel_udc_of_init()
/linux-4.4.14/drivers/isdn/mISDN/
H A Ddsp_cmx.c713 /* if members have two banks (and not on the same chip) */ dsp_cmx_hardware()
718 /* if both members have same slots with crossed banks */ dsp_cmx_hardware()
/linux-4.4.14/drivers/mfd/
H A Dab8500-debugfs.c1484 dev_err(dev, "debugfs error input > number of banks\n"); ab8500_bank_write()
3069 file = debugfs_create_file("all-banks", S_IRUGO, ab8500_dir, ab8500_debug_probe()
/linux-4.4.14/drivers/regulator/
H A Dtwl-regulator.c76 * The first three registers of all power resource banks help hardware to
/linux-4.4.14/drivers/spi/
H A Dspi-omap2-mcspi.c57 /* per-channel banks, 0x14 bytes each, first is: */
/linux-4.4.14/drivers/scsi/
H A Dgdth.h632 u8 mem_banks; /* memory banks */
/linux-4.4.14/drivers/leds/
H A Dleds-tca6507.c68 * defaulted. Similarly the banks know if each time was explicit or a
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c479 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
/linux-4.4.14/drivers/net/ethernet/realtek/
H A Datp.c98 Correction: the controller has two banks of 16 registers. The second
/linux-4.4.14/drivers/gpu/drm/i915/
H A Di915_gem_fence.c681 * banks of memory are paired and unswizzled on the i915_gem_detect_bit_6_swizzle()
/linux-4.4.14/drivers/clk/st/
H A Dclkgen-fsyn.c161 * generator found in STiH415 and STiH416 SYSCFG register banks. Note
/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h1492 #define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1493 #define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1494 #define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
/linux-4.4.14/arch/mips/include/asm/mach-au1x00/
H A Dau1000.h195 * Registers are 128bits (0x10 bytes), divided into 4 "banks".

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