Searched refs:bank_base (Results 1 – 3 of 3) sorted by relevance
237 static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base) in sunxi_irq_cfg_reg() argument242 return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg; in sunxi_irq_cfg_reg()251 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base) in sunxi_irq_ctrl_reg_from_bank() argument253 return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE; in sunxi_irq_ctrl_reg_from_bank()256 static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base) in sunxi_irq_ctrl_reg() argument260 return sunxi_irq_ctrl_reg_from_bank(bank, bank_base); in sunxi_irq_ctrl_reg()269 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base) in sunxi_irq_status_reg_from_bank() argument271 return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE; in sunxi_irq_status_reg_from_bank()274 static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base) in sunxi_irq_status_reg() argument278 return sunxi_irq_status_reg_from_bank(bank, bank_base); in sunxi_irq_status_reg()
68 void __iomem *bank_base[JZ_NAND_NUM_BANKS]; member96 chip->IO_ADDR_R = nand->bank_base[banknr]; in jz_nand_select_chip()97 chip->IO_ADDR_W = nand->bank_base[banknr]; in jz_nand_select_chip()109 void __iomem *bank_base = nand->bank_base[nand->selected_bank]; in jz_nand_cmd_ctrl() local116 bank_base += JZ_NAND_MEM_ADDR_OFFSET; in jz_nand_cmd_ctrl()118 bank_base += JZ_NAND_MEM_CMD_OFFSET; in jz_nand_cmd_ctrl()119 chip->IO_ADDR_W = bank_base; in jz_nand_cmd_ctrl()355 &nand->bank_base[bank - 1]); in jz_nand_detect_bank()402 nand->bank_base[bank - 1]); in jz_nand_detect_bank()531 nand->bank_base[bank - 1]); in jz_nand_probe()[all …]
926 void __iomem *bank_base; in alchemy_gpic_init_irq() local933 bank_base = AU1300_GPIC_ADDR + (i * 4); in alchemy_gpic_init_irq()934 __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); in alchemy_gpic_init_irq()936 __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); in alchemy_gpic_init_irq()