| /linux-4.4.14/drivers/staging/rtl8188eu/hal/ |
| D | odm_RTL8188E.c | 142 phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2); in dm_fast_training_init()
157 phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1); in dm_fast_training_init()
161 phy_set_bb_reg(adapter, 0x918, bMaskByte1, 5); in dm_fast_training_init()
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| D | rf.c | 119 phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); in rtl88eu_phy_rf6052_set_cck_txpower()
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| /linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phy.h | 59 #define bMaskByte1 0xff00 macro
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| D | rtl_dm.c | 1216 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); in _rtl92e_dm_bb_initialgain_restore()
1239 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); in _rtl92e_dm_bb_initialgain_restore()
1254 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); in rtl92e_dm_backup_state()
1349 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); in _rtl92e_dm_ctrl_initgain_byrssi_driver()
1382 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); in _rtl92e_dm_ctrl_initgain_byrssi_false_alarm()
1401 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); in _rtl92e_dm_ctrl_initgain_byrssi_false_alarm()
1452 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); in _rtl92e_dm_ctrl_initgain_byrssi_false_alarm()
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| D | r8192E_phyreg.h | 839 #define bMaskByte1 0xff00 macro
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| D | r8192E_phy.c | 1313 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); in rtl92e_init_gain()
1362 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); in rtl92e_init_gain()
1397 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); in rtl92e_init_gain()
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| /linux-4.4.14/drivers/staging/rtl8192u/ |
| D | r819xU_phy.h | 53 #define bMaskByte1 0xff00 macro
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| D | r8192U_dm.c | 1554 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ in dm_bb_initialgain_restore()
1569 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ in dm_bb_initialgain_restore()
1594 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ in dm_bb_initialgain_backup()
1768 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ in dm_ctrl_initgain_byrssi_by_driverrssi()
1807 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite.*/ in dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1840 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ in dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1934 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ in dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
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| D | r819xU_phy.c | 1721 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); in InitialGainOperateWorkItemCallBack()
1760 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); in InitialGainOperateWorkItemCallBack()
1789 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); in InitialGainOperateWorkItemCallBack()
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| D | r819xU_phyreg.h | 823 #define bMaskByte1 0xff00 macro
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| /linux-4.4.14/drivers/staging/rtl8723au/hal/ |
| D | rtl8723a_rf6052.c | 170 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); in rtl823a_phy_rf6052setccktxpower()
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| /linux-4.4.14/drivers/staging/rtl8712/ |
| D | rtl871x_mp_phy_regdef.h | 958 #define bMaskByte1 0xff00 macro
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| /linux-4.4.14/drivers/staging/rtl8188eu/include/ |
| D | rtw_mp_phy_regdef.h | 1012 #define bMaskByte1 0xff00 macro
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| D | Hal8188EPhyReg.h | 1047 #define bMaskByte1 0xff00 macro
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| /linux-4.4.14/drivers/staging/rtl8723au/include/ |
| D | Hal8723APhyReg.h | 984 #define bMaskByte1 0xff00 macro
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