H A D | hw.c | 77 alx_write_mem32(hw, ALX_MDIO_EXTN, val); alx_read_phy_core() 88 alx_write_mem32(hw, ALX_MDIO, val); alx_read_phy_core() 111 alx_write_mem32(hw, ALX_MDIO_EXTN, val); alx_write_phy_core() 124 alx_write_mem32(hw, ALX_MDIO, val); alx_write_phy_core() 302 alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START); alx_get_perm_macaddr() 314 alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START); alx_get_perm_macaddr() 330 alx_write_mem32(hw, ALX_STAD0, val); alx_set_macaddr() 332 alx_write_mem32(hw, ALX_STAD1, val); alx_set_macaddr() 341 alx_write_mem32(hw, ALX_MISC3, alx_reset_osc() 356 alx_write_mem32(hw, ALX_MISC, val); alx_reset_osc() 357 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); alx_reset_osc() 361 alx_write_mem32(hw, ALX_MSIC2, val2); alx_reset_osc() 362 alx_write_mem32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START); alx_reset_osc() 369 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); alx_reset_osc() 370 alx_write_mem32(hw, ALX_MISC, val); alx_reset_osc() 382 alx_write_mem32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN); alx_stop_mac() 384 alx_write_mem32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN); alx_stop_mac() 389 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_stop_mac() 413 alx_write_mem32(hw, ALX_MSIX_MASK, 0xFFFFFFFF); alx_reset_mac() 414 alx_write_mem32(hw, ALX_IMR, 0); alx_reset_mac() 415 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); alx_reset_mac() 422 alx_write_mem32(hw, ALX_RFD_PIDX, 1); alx_reset_mac() 428 alx_write_mem32(hw, ALX_PMCTRL, alx_reset_mac() 435 alx_write_mem32(hw, ALX_MASTER, alx_reset_mac() 457 alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS); alx_reset_mac() 460 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); alx_reset_mac() 469 alx_write_mem32(hw, ALX_MISC3, alx_reset_mac() 476 alx_write_mem32(hw, ALX_MISC, val); alx_reset_mac() 480 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_reset_mac() 483 alx_write_mem32(hw, ALX_SERDES, alx_reset_mac() 504 alx_write_mem32(hw, ALX_PHY_CTRL, val); alx_reset_phy() 506 alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT); alx_reset_phy() 520 alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN); alx_reset_phy() 575 alx_write_mem32(hw, ALX_WOL0, 0); alx_reset_pcie() 578 alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN); alx_reset_pcie() 583 alx_write_mem32(hw, ALX_UE_SVRT, val); alx_reset_pcie() 590 alx_write_mem32(hw, ALX_MASTER, alx_reset_pcie() 596 alx_write_mem32(hw, ALX_MASTER, alx_reset_pcie() 612 alx_write_mem32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN); alx_start_mac() 614 alx_write_mem32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN); alx_start_mac() 626 alx_write_mem32(hw, ALX_MAC_CTRL, mac); alx_start_mac() 641 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_cfg_mac_flowcontrol() 676 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); alx_enable_aspm() 772 alx_write_mem32(hw, ALX_DRV, val); alx_setup_speed_duplex() 928 alx_write_mem32(hw, ALX_RXQ0, ctrl); alx_disable_rss() 939 alx_write_mem32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL); alx_configure_basic() 943 alx_write_mem32(hw, ALX_IDLE_DECISN_TIMER, alx_configure_basic() 946 alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL); alx_configure_basic() 952 alx_write_mem32(hw, ALX_MASTER, val); alx_configure_basic() 953 alx_write_mem32(hw, ALX_IRQ_MODU_TIMER, alx_configure_basic() 956 alx_write_mem32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO); alx_configure_basic() 958 alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd); alx_configure_basic() 959 alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt); alx_configure_basic() 962 alx_write_mem32(hw, ALX_MTU, raw_mtu + 8); alx_configure_basic() 970 alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN); alx_configure_basic() 984 alx_write_mem32(hw, ALX_TXQ0, val); alx_configure_basic() 989 alx_write_mem32(hw, ALX_HQTPD, val); alx_configure_basic() 1001 alx_write_mem32(hw, ALX_RXQ2, alx_configure_basic() 1014 alx_write_mem32(hw, ALX_RXQ0, val); alx_configure_basic() 1023 alx_write_mem32(hw, ALX_DMA, val); alx_configure_basic() 1031 alx_write_mem32(hw, ALX_WRR, val); alx_configure_basic()
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