Searched refs:allowed_sclk_vddc_table (Results 1 – 2 of 2) sorted by relevance
3414 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_setup_default_dpm_tables() local3422 if (allowed_sclk_vddc_table == NULL) in ci_setup_default_dpm_tables()3424 if (allowed_sclk_vddc_table->count < 1) in ci_setup_default_dpm_tables()3450 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3453 allowed_sclk_vddc_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3455 allowed_sclk_vddc_table->entries[i].clk; in ci_setup_default_dpm_tables()3475 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3477 allowed_sclk_vddc_table->entries[i].v; in ci_setup_default_dpm_tables()3482 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()4885 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_set_private_data_variables_based_on_pptable() local[all …]
3550 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_setup_default_dpm_tables() local3558 if (allowed_sclk_vddc_table == NULL) in ci_setup_default_dpm_tables()3560 if (allowed_sclk_vddc_table->count < 1) in ci_setup_default_dpm_tables()3586 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3589 allowed_sclk_vddc_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3591 allowed_sclk_vddc_table->entries[i].clk; in ci_setup_default_dpm_tables()3611 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3613 allowed_sclk_vddc_table->entries[i].v; in ci_setup_default_dpm_tables()3618 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()5053 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_set_private_data_variables_based_on_pptable() local[all …]