Searched refs:allowed_mclk_table (Results 1 – 2 of 2) sorted by relevance
3416 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = in ci_setup_default_dpm_tables() local3426 if (allowed_mclk_table == NULL) in ci_setup_default_dpm_tables()3428 if (allowed_mclk_table->count < 1) in ci_setup_default_dpm_tables()3463 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3466 allowed_mclk_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3468 allowed_mclk_table->entries[i].clk; in ci_setup_default_dpm_tables()3484 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()3485 if (allowed_mclk_table) { in ci_setup_default_dpm_tables()3486 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3488 allowed_mclk_table->entries[i].v; in ci_setup_default_dpm_tables()[all …]
3552 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table = in ci_setup_default_dpm_tables() local3562 if (allowed_mclk_table == NULL) in ci_setup_default_dpm_tables()3564 if (allowed_mclk_table->count < 1) in ci_setup_default_dpm_tables()3599 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3602 allowed_mclk_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3604 allowed_mclk_table->entries[i].clk; in ci_setup_default_dpm_tables()3620 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()3621 if (allowed_mclk_table) { in ci_setup_default_dpm_tables()3622 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()3624 allowed_mclk_table->entries[i].v; in ci_setup_default_dpm_tables()[all …]