Home
last modified time | relevance | path

Searched refs:__reg (Results 1 – 21 of 21) sorted by relevance

/linux-4.4.14/arch/frv/include/asm/
Dirc-regs.h15 #define __reg(ADDR) (*(volatile unsigned long *)(ADDR)) macro
17 #define __get_TM0() ({ __reg(0xfeff9800); })
18 #define __get_TM1() ({ __reg(0xfeff9808); })
19 #define __set_TM1(V) do { __reg(0xfeff9808) = (V); mb(); } while(0)
24 unsigned long tm1 = __reg(0xfeff9808); \
27 __reg(0xfeff9808) = tm1; \
31 #define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; })
33 #define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0)
35 #define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; })
36 #define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0)
[all …]
Dgpio-regs.h15 #define __reg(ADDR) (*(volatile unsigned long *)(ADDR)) macro
17 #define __get_PDR() ({ __reg(0xfeff0400); })
18 #define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0)
20 #define __get_GPDR() ({ __reg(0xfeff0408); })
21 #define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0)
23 #define __get_SIR() ({ __reg(0xfeff0410); })
24 #define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0)
26 #define __get_SOR() ({ __reg(0xfeff0418); })
27 #define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0)
29 #define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0)
[all …]
Dserial-regs.h22 #define __get_UART0(R) ({ __reg(UART0_BASE + (R) * 8) >> 24; })
23 #define __get_UART1(R) ({ __reg(UART1_BASE + (R) * 8) >> 24; })
24 #define __set_UART0(R,V) do { __reg(UART0_BASE + (R) * 8) = (V) << 24; } while(0)
25 #define __set_UART1(R,V) do { __reg(UART1_BASE + (R) * 8) = (V) << 24; } while(0)
/linux-4.4.14/drivers/net/wireless/rt2x00/
Drt2x00reg.h246 #define SET_FIELD(__reg, __type, __field, __value)\ argument
249 *(__reg) &= ~((__field).bit_mask); \
250 *(__reg) |= ((__value) << \
255 #define GET_FIELD(__reg, __type, __field) \ argument
258 ((__reg) & ((__field).bit_mask)) >> \
262 #define rt2x00_set_field32(__reg, __field, __value) \ argument
263 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
264 #define rt2x00_get_field32(__reg, __field) \ argument
265 GET_FIELD(__reg, struct rt2x00_field32, __field)
267 #define rt2x00_set_field16(__reg, __field, __value) \ argument
[all …]
Drt2400pci.c51 #define WAIT_FOR_BBP(__dev, __reg) \ argument
52 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
53 #define WAIT_FOR_RF(__dev, __reg) \ argument
54 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
Drt2500usb.c139 #define WAIT_FOR_BBP(__dev, __reg) \ argument
140 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
141 #define WAIT_FOR_RF(__dev, __reg) \ argument
142 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
Drt61pci.c57 #define WAIT_FOR_BBP(__dev, __reg) \ argument
58 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
59 #define WAIT_FOR_RF(__dev, __reg) \ argument
60 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
61 #define WAIT_FOR_MCU(__dev, __reg) \ argument
63 H2M_MAILBOX_CSR_OWNER, (__reg))
Drt2500pci.c51 #define WAIT_FOR_BBP(__dev, __reg) \ argument
52 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
53 #define WAIT_FOR_RF(__dev, __reg) \ argument
54 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
Drt73usb.c58 #define WAIT_FOR_BBP(__dev, __reg) \ argument
59 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 #define WAIT_FOR_RF(__dev, __reg) \ argument
61 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
Drt2800lib.c58 #define WAIT_FOR_BBP(__dev, __reg) \ argument
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60 #define WAIT_FOR_RFCSR(__dev, __reg) \ argument
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \ argument
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64 #define WAIT_FOR_MCU(__dev, __reg) \ argument
66 H2M_MAILBOX_CSR_OWNER, (__reg))
/linux-4.4.14/drivers/mmc/host/
Ddw_mmc.h183 #define mci_fifo_readw(__reg) __raw_readw(__reg) argument
184 #define mci_fifo_readl(__reg) __raw_readl(__reg) argument
185 #define mci_fifo_readq(__reg) __raw_readq(__reg) argument
187 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) argument
188 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) argument
189 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) argument
223 #define __raw_writeq(__value, __reg) \ argument
224 (*(volatile u64 __force *)(__reg) = (__value))
225 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) argument
/linux-4.4.14/drivers/media/dvb-frontends/
Dstv090x_priv.h49 #define STV090x_READ_DEMOD(__state, __reg) (( \ argument
51 stv090x_read_reg(__state, STV090x_P2_##__reg) : \
52 stv090x_read_reg(__state, STV090x_P1_##__reg))
54 #define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \ argument
56 stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\
57 stv090x_write_reg(__state, STV090x_P1_##__reg, __data))
/linux-4.4.14/drivers/gpu/drm/armada/
Darmada_crtc.h21 struct armada_regs *__reg = _r; \
22 __reg[_i].offset = _o; \
23 __reg[_i].mask = ~(_m); \
24 __reg[_i].val = _v; \
/linux-4.4.14/arch/sparc/kernel/
Dprom_irqtrans.c83 #define sabre_read(__reg) \ argument
87 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
317 #define schizo_read(__reg) \ argument
321 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
325 #define schizo_write(__reg, __val) \ argument
328 : "r" (__val), "r" (__reg), \
Diommu.c34 #define iommu_read(__reg) \ argument
38 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
42 #define iommu_write(__reg, __val) \ argument
45 : "r" (__val), "r" (__reg), \
/linux-4.4.14/drivers/net/ethernet/cadence/
Dmacb.h449 #define macb_or_gem_writel(__bp, __reg, __value) \ argument
452 gem_writel((__bp), __reg, __value); \
454 macb_writel((__bp), __reg, __value); \
457 #define macb_or_gem_readl(__bp, __reg) \ argument
461 __v = gem_readl((__bp), __reg); \
463 __v = macb_readl((__bp), __reg); \
/linux-4.4.14/drivers/media/platform/s3c-camif/
Dcamif-regs.h160 #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) argument
/linux-4.4.14/drivers/pinctrl/spear/
Dpinctrl-plgpio.c649 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ argument
651 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
653 plgpio->csave_regs[i].__reg = \
654 _tmp | (plgpio->csave_regs[i].__reg & _mask); \
/linux-4.4.14/drivers/hwmon/
Dadt7411.c216 #define ADT7411_BIT_ATTR(__name, __reg, __bit) \ argument
218 adt7411_set_bit, __bit, __reg)
/linux-4.4.14/drivers/net/ethernet/sun/
Dsunhme.c244 #define hme_write32(__hp, __reg, __val) \ argument
245 ((__hp)->write32((__reg), (__val)))
246 #define hme_read32(__hp, __reg) \ argument
247 ((__hp)->read32(__reg))
265 #define hme_write32(__hp, __reg, __val) \ argument
266 sbus_writel((__val), (__reg))
267 #define hme_read32(__hp, __reg) \ argument
268 sbus_readl(__reg)
290 #define hme_write32(__hp, __reg, __val) \ argument
291 writel((__val), (__reg))
[all …]
/linux-4.4.14/arch/frv/kernel/
Dsetup.c785 __reg(UART0_BASE + UART_IER * 8) = 0; in setup_arch()
789 __reg(UART1_BASE + UART_IER * 8) = 0; in setup_arch()