Searched refs:__MASK (Results 1 – 4 of 4) sorted by relevance
62 #define __MASK(X) (1<<(X)) macro64 #define __MASK(X) (1UL<<(X)) macro68 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */69 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */70 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */78 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */79 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */80 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */81 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */82 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */[all …]
31 #define MSR_GS __MASK(MSR_GS_LG)32 #define MSR_UCLE __MASK(MSR_UCLE_LG)33 #define MSR_SPE __MASK(MSR_SPE_LG)34 #define MSR_DWE __MASK(MSR_DWE_LG)35 #define MSR_UBLE __MASK(MSR_UBLE_LG)36 #define MSR_IS __MASK(MSR_IS_LG)37 #define MSR_DS __MASK(MSR_DS_LG)38 #define MSR_PMM __MASK(MSR_PMM_LG)39 #define MSR_CM __MASK(MSR_CM_LG)
34 #define __MASK(x) ((1 << (x)) - 1) macro35 #define IRQ_MASK ((__MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) | \36 (__MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT))
329 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)