Searched refs:XTFPGA_CLKFRQ_VADDR (Results 1 - 3 of 3) sorted by relevance

/linux-4.4.14/arch/xtensa/platforms/xtfpga/include/platform/
H A Dserial.h16 #define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
H A Dhardware.h49 #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) macro
/linux-4.4.14/arch/xtensa/platforms/xtfpga/
H A Dsetup.c106 *(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR); update_clock_frequency()
182 clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR; platform_calibrate_ccount()
319 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR; xtavnet_init()
329 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR; xtavnet_init()

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