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Searched refs:XCHAL_ICACHE_LINEWIDTH (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/arch/xtensa/include/asm/
Dcacheasm.h88 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
125 XCHAL_ICACHE_LINEWIDTH
162 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
199 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
Dcache.h23 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
/linux-4.4.14/arch/xtensa/variants/fsf/include/variant/
Dcore.h116 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro
/linux-4.4.14/arch/xtensa/variants/dc232b/include/variant/
Dcore.h123 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/linux-4.4.14/arch/xtensa/variants/dc233c/include/variant/
Dcore.h162 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/linux-4.4.14/arch/xtensa/variants/de212/include/variant/
Dcore.h210 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro