Searched refs:WRITE_DATA_DST_SEL (Results 1 – 8 of 8) sorted by relevance
143 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
257 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
4418 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()4426 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()4434 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()4442 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()4558 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v8_0_ring_emit_ib_gfx()4597 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v8_0_ring_emit_ib_compute()4702 WRITE_DATA_DST_SEL(0)) | in gfx_v8_0_ring_emit_vm_flush()4718 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_vm_flush()
2580 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v7_0_ring_emit_ib_gfx()2618 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v7_0_ring_emit_ib_compute()3654 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_vm_flush()3668 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_vm_flush()4711 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4719 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4727 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4735 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
1635 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
4164 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()6117 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()6131 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()6138 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()6149 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()6160 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1730 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5069 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5084 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5092 WRITE_DATA_DST_SEL(0))); in si_vm_flush()