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Searched refs:WREG32_SMC (Results 1 – 21 of 21) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dtrinity_smc.c67 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
69 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
76 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
83 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
Dtrinity_dpm.c382 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
506 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
524 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
529 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
533 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
537 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
598 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
608 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
620 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
632 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()
[all …]
Dci_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
Dsi_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
Dci_dpm.c597 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
881 WREG32_SMC(CG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
888 WREG32_SMC(CG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
905 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
914 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
941 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
945 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1119 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
1196 WREG32_SMC(CG_TACH_CTRL, tmp);
1212 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
[all …]
Dkv_dpm.c275 WREG32_SMC(local_cac_reg->cntl, data);
315 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
406 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
407 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
410 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
411 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
414 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
415 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
418 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
419 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
[all …]
Dcik.c9725 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9772 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
10045 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
10051 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
10056 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
10061 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
10067 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
Dsi.c5453 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5454 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5465 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5466 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
Dradeon.h2542 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2576 WREG32_SMC(reg, tmp_); \
Dsi_dpm.c2763 WREG32_SMC(offset, data); in si_program_cac_config_registers()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dfiji_smc.c351 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
355 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
431 WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0); in fiji_smu_request_load_fw()
570 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in fiji_smu_start_in_protection_mode()
577 WREG32_SMC(ixSMU_STATUS, 0); in fiji_smu_start_in_protection_mode()
582 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); in fiji_smu_start_in_protection_mode()
587 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in fiji_smu_start_in_protection_mode()
592 WREG32_SMC(ixSMU_INPUT_DATA, val); in fiji_smu_start_in_protection_mode()
595 WREG32_SMC(ixFIRMWARE_FLAGS, 0); in fiji_smu_start_in_protection_mode()
671 WREG32_SMC(ixFIRMWARE_FLAGS, 0); in fiji_smu_start_in_non_protection_mode()
[all …]
Dtonga_smc.c351 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
355 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
433 WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0); in tonga_smu_request_load_fw()
572 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in tonga_smu_start_in_protection_mode()
579 WREG32_SMC(ixSMU_STATUS, 0); in tonga_smu_start_in_protection_mode()
584 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); in tonga_smu_start_in_protection_mode()
589 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in tonga_smu_start_in_protection_mode()
594 WREG32_SMC(ixSMU_INPUT_DATA, val); in tonga_smu_start_in_protection_mode()
597 WREG32_SMC(ixFIRMWARE_FLAGS, 0); in tonga_smu_start_in_protection_mode()
672 WREG32_SMC(ixFIRMWARE_FLAGS, 0); in tonga_smu_start_in_non_protection_mode()
[all …]
Dci_smc.c122 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_start_smc()
130 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_reset_smc()
146 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_ci_stop_smc_clock()
155 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_ci_start_smc_clock()
Dci_dpm.c715 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
998 WREG32_SMC(ixCG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
1005 WREG32_SMC(ixCG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
1022 WREG32_SMC(ixCG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
1031 WREG32_SMC(ixCG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
1059 WREG32_SMC(ixCG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1063 WREG32_SMC(ixCG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1244 WREG32_SMC(ixCG_FDO_CTRL0, tmp); in ci_dpm_set_fan_speed_percent()
1322 WREG32_SMC(CG_TACH_CTRL, tmp);
1338 WREG32_SMC(ixCG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
[all …]
Diceland_smc.c129 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in iceland_start_smc()
137 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in iceland_reset_smc()
153 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); in iceland_stop_smc_clock()
161 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); in iceland_start_smc_clock()
308 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, val | 1); in iceland_smu_upload_firmware_image()
Dkv_dpm.c408 WREG32_SMC(local_cac_reg->cntl, data);
448 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
539 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
540 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
543 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
544 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
547 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
548 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
551 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
552 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
[all …]
Dcik.c917 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
928 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1500 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1549 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1835 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1843 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1848 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1853 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1859 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
Dvi.c366 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
377 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
988 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
Damdgpu_cgs.c334 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
Dcz_dpm.c980 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0); in cz_program_voting_clients()
985 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); in cz_clear_voting_clients()
Damdgpu.h2151 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro