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Searched refs:VM_CONTEXT1_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dgmc_v8_0.c548 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
550 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
552 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
554 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
556 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
558 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
668 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
669 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v8_0_gart_enable()
670 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
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Dgmc_v7_0.c487 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
489 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
491 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
493 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
495 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
497 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
589 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
590 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v7_0_gart_enable()
591 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v7_0_gart_enable()
/linux-4.4.14/drivers/gpu/drm/radeon/
Dnid.h143 #define VM_CONTEXT1_CNTL 0x1414 macro
Dni.c1339 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
1373 WREG32(VM_CONTEXT1_CNTL, 0); in cayman_pcie_gart_disable()
Dsid.h408 #define VM_CONTEXT1_CNTL 0x1414 macro
Dcikd.h528 #define VM_CONTEXT1_CNTL 0x1414 macro
Devergreen.c2542 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_enable()
2558 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_disable()
2608 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_agp_enable()
Devergreend.h1140 #define VM_CONTEXT1_CNTL 0x1414 macro
Dsi.c4342 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
4380 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
Dcik.c5909 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5982 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()