Searched refs:VCLK_SRC_SEL_MASK (Results 1 – 10 of 10) sorted by relevance
59 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()125 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
58 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
142 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
363 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
1576 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
205 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()283 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
1193 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()1266 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
7330 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()7404 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
919 #define VCLK_SRC_SEL_MASK 0x03 macro
1392 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()1452 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()