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Searched refs:UVD_RBC_RB_CNTL (Results 1 – 4 of 4) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
397 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v6_0_start()
398 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in uvd_v6_0_start()
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); in uvd_v6_0_start()
400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v6_0_start()
401 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in uvd_v6_0_start()
Duvd_v5_0.c396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
397 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v5_0_start()
398 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in uvd_v5_0_start()
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); in uvd_v5_0_start()
400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v5_0_start()
401 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in uvd_v5_0_start()
/linux-4.4.14/drivers/gpu/drm/radeon/
Duvd_v1_0.c357 WREG32(UVD_RBC_RB_CNTL, 0x11010101); in uvd_v1_0_start()
378 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
393 WREG32(UVD_RBC_RB_CNTL, 0x11010101); in uvd_v1_0_stop()
Dr600d.h1545 #define UVD_RBC_RB_CNTL 0xf6a4 macro