Searched refs:UTMIP_PLL_CFG1 (Results 1 – 4 of 4) sorted by relevance
123 #define UTMIP_PLL_CFG1 0x484 macro1002 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()1017 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()1026 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()1029 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
109 #define UTMIP_PLL_CFG1 0x484 macro1061 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()1076 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()1085 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()1088 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
128 #define UTMIP_PLL_CFG1 0x484 macro902 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()917 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()
88 #define UTMIP_PLL_CFG1 0x804 macro420 val = readl(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()425 writel(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()