Searched refs:UART011_MIS (Results 1 – 2 of 2) sorted by relevance
55 #define UART011_MIS 0x40 /* Masked interrupt status. */ macro
1480 writew(readw(regs + UART011_MIS), regs + UART011_ICR); in pl011_quiesce_irqs()1579 writew(0xff, uap->port.membase + UART011_MIS); in pl011_write_lcr_h()