Searched refs:TX49XX_ICACHE_INDEX_INV_WAR (Results 1 - 15 of 15) sorted by relevance

/linux-4.4.14/arch/mips/include/asm/mach-cavium-octeon/
H A Dwar.h20 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-generic/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-ip22/
H A Dwar.h23 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-ip27/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-ip28/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-ip32/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-malta/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-rc32434/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-rm/
H A Dwar.h23 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-sead3/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/mach-tx49xx/
H A Dwar.h19 #define TX49XX_ICACHE_INDEX_INV_WAR 1 macro
/linux-4.4.14/arch/mips/include/asm/mach-sibyte/
H A Dwar.h34 #define TX49XX_ICACHE_INDEX_INV_WAR 0 macro
/linux-4.4.14/arch/mips/include/asm/
H A Dwar.h207 #ifndef TX49XX_ICACHE_INDEX_INV_WAR
208 #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
/linux-4.4.14/arch/mips/mm/
H A Dc-r4k.c209 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
336 else if (TX49XX_ICACHE_INDEX_INV_WAR) r4k_blast_icache_page_indexed_setup()
363 else if (TX49XX_ICACHE_INDEX_INV_WAR) r4k_blast_icache_setup()

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