Searched refs:TWI1_CLKDIV (Results 1 – 6 of 6) sorted by relevance
56 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ macro
95 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ macro
692 #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ macro708 #define TWI1_REGBASE TWI1_CLKDIV
1870 .start = TWI1_CLKDIV,1871 .end = TWI1_CLKDIV + 0xFF,
1546 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV) in bfin_debug_mmrs_init()1554 # ifdef TWI1_CLKDIV in bfin_debug_mmrs_init()
616 #define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */ macro