Searched refs:TWI1 (Results 1 - 10 of 10) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/
H A Dirq.h57 #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
H A DdefBF538.h693 #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
700 #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
701 #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
1282 #define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h49 #define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
H A DdefBF60x_base.h614 TWI1
616 #define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
617 #define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
618 #define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
619 #define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
620 #define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
621 #define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
622 #define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
623 #define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
624 #define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
625 #define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
626 #define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
627 #define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
628 #define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
629 #define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
630 #define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
631 #define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Dirq.h60 #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
H A DcdefBF547.h154 /* Two Wire Interface Registers (TWI1) */
H A DcdefBF544.h82 /* Two Wire Interface Registers (TWI1) */
H A DdefBF544.h53 /* Two Wire Interface Registers (TWI1) */
H A DdefBF547.h92 /* Two Wire Interface Registers (TWI1) */
H A DdefBF54x_base.h1562 #define TWI1 0x4000 /* TWI1 */ macro

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