Searched refs:TSTT (Results 1 – 7 of 7) sorted by relevance
| /linux-4.4.14/arch/metag/tbx/ |
| D | tbictx.S | 41 TSTT D0Ar2,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XCBF_BIT
45 TSTT D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT /* Is catch state dirty? */
101 TSTT D0Ar2,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT
106 TSTT D0Ar2,#TBICTX_XEXT_BIT /* Extended base-state model? */
115 TSTT D0Ar2,#TBICTX_XDX8_BIT /* Save extended DX regs? */
122 TSTT D0Ar2,#TBICTX_XAXX_BIT /* Save extended AX regs? */
130 TSTT D0Ar2,#TBICTX_XHL2_BIT /* Save hardware-loop regs? */
150 TSTT D0Ar2,#TBICTX_XTDP_BIT /* Save per-thread DSP regs? */
204 TSTT D0Ar2,#TBICTX_XCBF_BIT /* Want to save CBUF? */
211 TSTT D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT /* Need to save CBUF? */
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| D | tbictxfpu.S | 43 TSTT D0Ar2,#TBICTX_FPAC_BIT
78 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
135 TSTT D0Ar2,#TBICTX_FPAC_BIT
162 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
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| D | tbipcx.S | 149 TSTT D1Ar1,#HI(TXDIVTIME_RPDIRTY_BIT)/* NZ = RPDIRTY */
158 TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
180 TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
254 TSTT D0Re0,#TBICTX_WAIT_BIT /* Do we WAIT anyway? */
381 TSTT D1Ar1,#HI(0x00800000)
386 TSTT D1Ar3,#HI(0x00100000 >> 1)
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| D | tbiroot.S | 46 TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Bgnd or Int level? */
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| D | tbitimer.S | 177 TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Interrupt level timer? */
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| /linux-4.4.14/arch/metag/lib/ |
| D | div64.S | 81 TSTT D1Ar1,#HI(0x80000000)
88 TSTT D1Ar3,#HI(0x80000000)
96 TSTT D1.5,#HI(0x80000000) define
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| /linux-4.4.14/arch/metag/kernel/ |
| D | tbiunexp.S | 9 TSTT D0Ar2,#TBICTX_CRIT_BIT ! Result of nestable int call?
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