| /linux-4.4.14/drivers/staging/rtl8712/ |
| H A D | rtl8712_gp_regdef.h | 30 #define TIMER1 (RTL8712_GP_ + 0x04) macro
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| /linux-4.4.14/arch/arc/kernel/ |
| H A D | time.c | 20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
26 * while TIMER1 for free running (clocksource)
28 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
156 * set 32bit TIMER1 to keep counting monotonically and wraparound
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| /linux-4.4.14/arch/arm/mach-gemini/ |
| H A D | time.c | 146 /* Use TIMER1 as clock event */
148 .name = "TIMER1",
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| /linux-4.4.14/drivers/clk/ |
| H A D | clk-efm32gg.c | 53 clk[clk_HFPERCLKTIMER1] = clk_register_gate(NULL, "HFPERCLK.TIMER1", efm32gg_cmu_init()
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| /linux-4.4.14/arch/m68k/include/asm/ |
| H A D | m54xxsim.h | 53 #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
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| H A D | m5206sim.h | 93 #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
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| H A D | m520xsim.h | 158 #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
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| H A D | m5272sim.h | 86 #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
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| H A D | m5407sim.h | 85 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
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| H A D | m5307sim.h | 102 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
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| H A D | m5441xsim.h | 97 #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
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| H A D | m525xsim.h | 96 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
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| H A D | m53xxsim.h | 120 #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
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| /linux-4.4.14/drivers/pinctrl/ |
| H A D | pinctrl-lpc18xx.c | 283 LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
284 LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
285 LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
286 LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
287 LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
288 LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
289 LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
290 LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
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| /linux-4.4.14/arch/arm/mach-spear/ |
| H A D | time.c | 29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
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| /linux-4.4.14/drivers/irqchip/ |
| H A D | irq-s3c24xx.c | 648 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
717 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
819 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
997 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| H A D | reg.h | 250 #define TIMER1 0x02E8 macro
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| /linux-4.4.14/arch/blackfin/mach-bf609/include/mach/ |
| H A D | defBF60x_base.h | 505 #define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
506 #define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
507 #define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
508 #define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
509 #define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
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| /linux-4.4.14/drivers/tty/ |
| H A D | synclinkmp.c | 382 #define TIMER1 0x08 macro
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| /linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
| H A D | defBF54x_base.h | 1603 #define TIMER1 0x800000 /* Timer 1 */ macro
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