Searched refs:TILE_SPLIT (Results 1 – 11 of 11) sorted by relevance
61 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro1350 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()1356 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()1362 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v8_0_tiling_mode_table_init()1368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v8_0_tiling_mode_table_init()1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()1380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()1386 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()1616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()1622 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1033 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v7_0_tiling_mode_table_init()1045 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v7_0_tiling_mode_table_init()1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v7_0_tiling_mode_table_init()1058 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1069 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1072 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1097 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1123 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1155 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
188 # define TILE_SPLIT(x) ((x) << 11) macro
520 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
2110 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
2168 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2180 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2469 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2489 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in si_tiling_mode_table_init()2499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2519 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2529 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2539 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2559 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()[all …]
2377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2383 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2389 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2395 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); in cik_tiling_mode_table_init()2401 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2418 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2606 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2612 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()[all …]
1197 # define TILE_SPLIT(x) ((x) << 11) macro
1242 # define TILE_SPLIT(x) ((x) << 11) macro