Searched refs:Start (Results 1 - 200 of 1926) sorted by relevance

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/linux-4.4.14/drivers/vhost/
H A Dtest.h4 /* Start a given test on the virtio null device. 0 stops all tests. */
/linux-4.4.14/arch/m32r/include/asm/
H A Ds1d13806.h42 {0x0035,0x01}, // TFT FPLINE Start Position Register
47 {0x003B,0x0A}, // TFT FPFRAME Start Position Register
51 {0x0042,0x00}, // LCD Display Start Address Register 0
52 {0x0043,0x00}, // LCD Display Start Address Register 1
53 {0x0044,0x00}, // LCD Display Start Address Register 2
75 {0x0035,0x01}, // TFT FPLINE Start Position Register
80 {0x003B,0x07}, // TFT FPFRAME Start Position Register
85 {0x0042,0x00}, // LCD Display Start Address Register 0
86 {0x0043,0x00}, // LCD Display Start Address Register 1
87 {0x0044,0x00}, // LCD Display Start Address Register 2
91 {0x0042,0xC0}, // LCD Display Start Address Register 0
92 {0x0043,0x02}, // LCD Display Start Address Register 1
93 {0x0044,0x00}, // LCD Display Start Address Register 2
109 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
114 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
118 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
119 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
120 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
126 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
139 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
155 {0x0104,0x00}, // BitBlt Source Start Address Register 0
156 {0x0105,0x00}, // BitBlt Source Start Address Register 1
157 {0x0106,0x00}, // BitBlt Source Start Address Register 2
158 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
159 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
160 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
/linux-4.4.14/drivers/md/
H A Draid0.h5 sector_t zone_end; /* Start of the next zone (in sectors) */
/linux-4.4.14/arch/cris/boot/rescue/
H A Dhead_v32.S19 ;; Start clocks for used blocks.
/linux-4.4.14/arch/avr32/kernel/
H A Dhead.S17 /* Start the show */
/linux-4.4.14/include/video/
H A Ds1d13xxxfb.h46 #define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */
51 #define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
65 #define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */
70 #define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */
74 #define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
75 #define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
76 #define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
83 #define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
96 #define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
112 #define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
113 #define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
114 #define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
115 #define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
116 #define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
117 #define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
H A Dcirrus.h102 #define CL_GR28 0x28 /* BLT Destination Start Low */
103 #define CL_GR29 0x29 /* BLT Destination Start Mid */
104 #define CL_GR2A 0x2a /* BLT Destination Start High */
105 #define CL_GR2C 0x2c /* BLT Source Start Low */
106 #define CL_GR2D 0x2d /* BLT Source Start Mid */
107 #define CL_GR2E 0x2e /* BLT Source Start High */
110 #define CL_GR31 0x31 /* BLT Start/Status */
/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/
H A DdefBF539.h62 #define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
68 #define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
74 #define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
80 #define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
86 #define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
92 #define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
98 #define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
104 #define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
110 #define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
112 #define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
116 #define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
118 #define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
121 #define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
/linux-4.4.14/arch/s390/kernel/
H A Dhead_kdump.S31 jne .Lrelocate # No : Start data mover
32 lghi %r2,0 # Yes: Start kdump kernel
77 basr %r14,%r14 # Start relocated kernel
88 0: lpswe .Lrestart_psw-0b(%r13) # Start new kernel...
H A Dvmlinux.lds.S49 _sdata = .; /* Start of data section */
/linux-4.4.14/include/linux/
H A Dinterval_tree.h8 unsigned long start; /* Start of interval */
H A Dkern_levels.h4 #define KERN_SOH "\001" /* ASCII Start Of Header */
H A Ddm-region-hash.h99 /* Start/stop recovery. */
H A Di2c-algo-pca.h50 #define I2C_PCA_CON_STA 0x20 /* Start */
H A Dpxa2xx_ssp.h163 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
164 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
171 #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
H A Dof_platform.h23 * @phys_addr: Start address of registers to match against node
H A Datmel_serial.h27 #define ATMEL_US_STTBRK BIT(9) /* Start Break */
29 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */
/linux-4.4.14/arch/m68k/coldfire/
H A Dfirebee.c29 #define PART_BOOT_START 0x00000000 /* Start at bottom of flash */
31 #define PART_IMAGE_START 0x00040000 /* Start after boot loader */
33 #define PART_FPGA_START 0x00700000 /* Start at offset 7MB */
/linux-4.4.14/arch/sh/include/asm/
H A Dhd64461.h66 #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
96 #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
97 #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
102 #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
103 #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
107 #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
111 #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
112 #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
113 #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
114 #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
117 #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
118 #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
119 #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
120 #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
/linux-4.4.14/arch/arm/mach-sa1100/
H A Djornada720.c78 {0x0035,0x01}, // TFT FPLINE Start Position Register
83 {0x003B,0x0B}, // TFT FPFRAME Start Position Register
87 {0x0042,0x00}, // LCD Display Start Address Register 0
88 {0x0043,0x00}, // LCD Display Start Address Register 1
89 {0x0044,0x00}, // LCD Display Start Address Register 2
97 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
102 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
106 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
107 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
108 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
115 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
128 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
144 {0x0104,0x00}, // BitBlt Source Start Address Register 0
145 {0x0105,0x00}, // BitBlt Source Start Address Register 1
146 {0x0106,0x00}, // BitBlt Source Start Address Register 2
147 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
148 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
149 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A DdefBF549.h65 #define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
73 #define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
81 #define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
89 #define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
97 #define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
105 #define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
113 #define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
121 #define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
129 #define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
131 #define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
137 #define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
139 #define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
144 #define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
H A DdefBF54x_base.h208 #define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
224 #define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
240 #define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
256 #define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
272 #define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
288 #define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
304 #define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
320 #define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
336 #define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
352 #define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
368 #define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
384 #define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
400 #define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
413 #define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
429 #define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
442 #define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
698 #define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
714 #define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
730 #define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
746 #define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
762 #define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
778 #define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
794 #define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
810 #define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
826 #define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
842 #define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
858 #define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
874 #define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
890 #define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
903 #define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
919 #define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
932 #define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
/linux-4.4.14/include/linux/spi/
H A Dadi_spi3.h48 #define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
131 #define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */
132 #define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */
142 #define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */
143 #define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */
153 #define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
154 #define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
165 #define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
166 #define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
191 #define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
192 #define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
202 #define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
203 #define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
/linux-4.4.14/fs/nfs/
H A Dnfs4getroot.c23 /* Start by getting the root filehandle from the server */ nfs4_get_rootfh()
/linux-4.4.14/include/linux/platform_data/
H A Dusb-pxa3xx-ulpi.h28 /* Start PXA3xx U2D host */
/linux-4.4.14/arch/sparc/include/uapi/asm/
H A Dwatchdog.h18 #define WIOCSTART _IO (WATCHDOG_IOCTL_BASE, 10) /* Start Timer */
/linux-4.4.14/tools/lib/lockdep/uinclude/linux/
H A Dkern_levels.h4 #define KERN_SOH "" /* ASCII Start Of Header */
/linux-4.4.14/arch/c6x/kernel/
H A Dvmlinux.lds.S28 * Start kernel read only segment
103 * Start kernel read-write segment.
/linux-4.4.14/arch/blackfin/include/asm/
H A Dpda.h25 unsigned long *ipdt; /* Start of switchable I-CPLB table */
27 unsigned long *dpdt; /* Start of switchable D-CPLB table */
H A Dbfin_sdh.h75 #define START_BIT_ERR (1 << 9) /* Start Bit Error */
99 #define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
112 #define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
/linux-4.4.14/drivers/net/ethernet/amd/
H A Dni65.h33 #define CSR0_STRT 0x0002 /* Start (RS) */
61 #define RCV_START 0x02 /* Start of Packet */
74 #define XMIT_START 0x02 /* Start of Packet */
H A Da2065.h74 #define LE_C0_STRT 0x0002 /* Start */
132 #define LE_R1_SOP 0x02 /* Start of Packet */
148 #define LE_T1_SOP 0x02 /* Start of Packet */
H A Dariadne.h193 #define STRT 0x0200 /* Start */
229 #define TXSTRT 0x0800 /* Transmit Start Status */
230 #define TXSTRTM 0x0400 /* Transmit Start Mask */
317 #define RF_STP 0x0002 /* Start of Packet */
331 #define TF_STP 0x0002 /* Start of Packet */
H A D7990.h155 #define LE_C0_STRT 0x0002 /* Start */
203 #define LE_R1_SOP 0x02 /* Start of Packet */
217 #define LE_T1_SOP 0x02 /* Start of Packet */
/linux-4.4.14/Documentation/mic/mpssd/
H A Dmpss20 # mpss Start mpssd.
27 # Required-Start:
62 # Start the daemon
/linux-4.4.14/drivers/usb/dwc3/
H A Ddebug.h33 return "Start New Configuration"; dwc3_gadget_ep_cmd_string()
39 return "Start Transfer"; dwc3_gadget_ep_cmd_string()
147 return "Start-Of-Frame"; dwc3_gadget_event_string()
205 return "Start of Frame"; dwc3_gadget_event_type_string()
/linux-4.4.14/drivers/staging/fbtft/
H A Dfb_ssd1306.c72 /* Set Display Start Line */ init_display()
128 /* Set Lower Column Start Address for Page Addressing Mode */ set_addr_win()
130 /* Set Higher Column Start Address for Page Addressing Mode */ set_addr_win()
132 /* Set Display Start Line */ set_addr_win()
H A Dfb_ili9320.c58 /* *********** Start Initial Sequence ********* */ init_display()
62 /* Start internal OSC. */ init_display()
133 /* Horizontal GRAM Start Address */ init_display()
139 /* Vertical GRAM Start Address */ init_display()
177 /* R20h = Horizontal GRAM Start Address */ set_addr_win()
178 /* R21h = Vertical GRAM Start Address */ set_addr_win()
H A Dfb_ili9325.c111 /* ----------- Start Initial Sequence ----------- */ init_display()
145 write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ init_display()
147 write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ init_display()
148 write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ init_display()
172 /* R20h = Horizontal GRAM Start Address */ set_addr_win()
173 /* R21h = Vertical GRAM Start Address */ set_addr_win()
H A Dfb_bd663474.c120 /* R200h = Horizontal GRAM Start Address */ set_addr_win()
121 /* R201h = Vertical GRAM Start Address */ set_addr_win()
H A Dfb_s6d1121.c84 /* R20h = Horizontal GRAM Start Address */ set_addr_win()
85 /* R21h = Vertical GRAM Start Address */ set_addr_win()
H A Dfbtft-io.c146 /* Start writing by pulling down /WR */ fbtft_write_gpio8_wr()
196 /* Start writing by pulling down /WR */ fbtft_write_gpio16_wr()
H A Dfb_upd161704.c129 /* R20h = Horizontal GRAM Start Address */ set_addr_win()
130 /* R21h = Vertical GRAM Start Address */ set_addr_win()
/linux-4.4.14/arch/sparc/prom/
H A Dbootstr_32.c29 /* Start from 1 and go over fd(0,0,0)kernel */ prom_getbootargs()
H A Dmp.c17 /* Start cpu with prom-tree node 'cpunode' using context described
/linux-4.4.14/arch/alpha/kernel/
H A Dvmlinux.lds.S51 _sdata = .; /* Start of rw data section */
/linux-4.4.14/samples/pktgen/
H A Dpktgen.conf-1-1-flows17 # Config Start Here -----------------------------------------------------------
H A Dpktgen.conf-1-1-ip617 # Config Start Here -----------------------------------------------------------
H A Dpktgen.conf-1-1-ip6-rdos17 # Config Start Here -----------------------------------------------------------
H A Dpktgen.conf-1-1-rdos17 # Config Start Here -----------------------------------------------------------
H A Dpktgen.conf-1-217 # Config Start Here -----------------------------------------------------------
/linux-4.4.14/include/linux/mtd/
H A Donenand_regs.h95 * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
102 * Start Address 8 F107h (R/W)
110 * Start Buffer Register F200h (R/W)
/linux-4.4.14/arch/m32r/kernel/
H A Dvmlinux.lds.S47 _sdata = .; /* Start of data section */
/linux-4.4.14/arch/arm/mach-lpc32xx/include/mach/
H A Dhardware.h21 * Start of virtual addresses for IO devices
/linux-4.4.14/drivers/vfio/platform/reset/
H A Dvfio_platform_calxedaxgmac.c41 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
42 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
H A Dregs-lan.h26 #define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */
27 #define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */
H A Dregs-wan.h26 #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */
27 #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */
/linux-4.4.14/drivers/video/fbdev/
H A Dtmiofb.c128 #define LCR_CFSAL 0x00a /* Command FIFO Start Address Low */
129 #define LCR_CFSAH 0x00c /* Command FIFO Start Address High */
147 #define LCR_GDSAL 0x122 /* Graphics Display Start Address Low */
148 #define LCR_GDSAH 0x124 /* Graphics Display Start Address High */
153 #define LCR_HDS 0x142 /* Horizontal Display Start */
154 #define LCR_HSS 0x144 /* H-Sync Start */
158 #define LCR_VDS 0x152 /* Vertical Display Start */
159 #define LCR_VSS 0x154 /* V-Sync Start */
165 #define LCR_VIHSS 0x16a /* Video Interface H-Sync Start */
166 #define LCR_VIVS 0x16c /* Video Interface Vertical Start */
168 #define LCR_VIVSS 0x170 /* Video Interface V-Sync Start */
170 #define LCR_VIDWSAL 0x180 /* VI Data Write Start Address Low */
171 #define LCR_VIDWSAH 0x182 /* VI Data Write Start Address High */
172 #define LCR_VIDRSAL 0x184 /* VI Data Read Start Address Low */
173 #define LCR_VIDRSAH 0x186 /* VI Data Read Start Address High */
174 #define LCR_VIPDDST 0x188 /* VI Picture Data Display Start Timing */
185 #define LCR_STHS 0x1a8 /* STH Start */
187 #define LCR_YCKSW 0x1ac /* YCK Start Wait */
188 #define LCR_YSTS 0x1ae /* YST Start */
189 #define LCR_PPOLS 0x1b0 /* #PPOL Start */
H A Dw100fb.h23 /* Block CIF Start: */
53 /* Block CP Start: */
60 /* Block DISPLAY Start: */
124 /* Block GFX Start: */
155 /* Block IDCT Start: */
163 /* Block MC Start: */
180 /* Block BM Start: */
196 /* Block RBBM Start: */
204 /* Block CG Start: */
H A Dasiliantfb.c379 {0x0c, 0x00}, /* Start address high */
380 {0x0d, 0x00}, /* Start address low */
381 {0x40, 0x00}, /* Extended Start Address */
382 {0x41, 0x00}, /* Extended Start Address */
H A Dcg14.c114 u16 hbs; /* Hor Blank Start */
116 u16 hss; /* Hor Sync Start */
119 u16 vbs; /* Vert Blank Start */
121 u16 vss; /* Vert Sync Start */
/linux-4.4.14/drivers/media/pci/cx25821/
H A Dcx25821-sram.h26 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
31 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers */
40 /* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */
43 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
50 /* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A DdefBF60x_base.h1521 #define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
1523 #define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
1525 #define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
1542 #define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
1544 #define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
1546 #define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
1563 #define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
1565 #define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
1567 #define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
1584 #define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
1586 #define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
1588 #define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
1605 #define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
1607 #define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
1609 #define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
1626 #define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
1628 #define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
1630 #define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
1647 #define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
1649 #define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
1651 #define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
1668 #define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
1670 #define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
1672 #define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
1689 #define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
1691 #define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
1693 #define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
1710 #define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
1712 #define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
1714 #define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
1731 #define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
1733 #define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
1735 #define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
1752 #define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
1754 #define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
1756 #define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
1773 #define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
1775 #define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
1777 #define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
1794 #define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
1796 #define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
1798 #define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
1815 #define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
1817 #define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
1819 #define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
1836 #define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
1838 #define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
1840 #define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
1857 #define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
1859 #define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
1861 #define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
1878 #define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
1880 #define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
1882 #define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
1899 #define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
1901 #define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
1903 #define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
1920 #define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
1922 #define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
1924 #define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
1941 #define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
1943 #define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
1945 #define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
1962 #define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
1964 #define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
1966 #define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
1983 #define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
1985 #define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
1987 #define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
2004 #define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
2006 #define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
2008 #define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
2025 #define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
2027 #define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
2029 #define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
2046 #define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
2048 #define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
2050 #define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
2067 #define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
2069 #define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
2071 #define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
2088 #define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
2090 #define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
2092 #define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
2109 #define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
2111 #define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
2113 #define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
2130 #define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
2132 #define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
2134 #define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
2151 #define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
2153 #define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
2155 #define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
2172 #define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
2174 #define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
2176 #define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
2193 #define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
2195 #define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
2197 #define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
2214 #define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
2216 #define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
2218 #define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
2235 #define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
2237 #define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
2239 #define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
2256 #define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
2258 #define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
2260 #define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
2277 #define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
2279 #define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
2281 #define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
2298 #define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
2300 #define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
2302 #define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
2319 #define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
2321 #define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
2323 #define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
2340 #define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
2342 #define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
2344 #define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
2361 #define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
2363 #define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
2365 #define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
2382 #define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
2384 #define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
2386 #define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
2403 #define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
2405 #define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
2407 #define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
2424 #define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
2426 #define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
2428 #define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
2445 #define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
2447 #define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
2449 #define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
2466 #define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
2468 #define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
2470 #define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
2487 #define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
2489 #define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
2491 #define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
H A DdefBF609.h24 #define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
26 #define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
29 #define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
31 #define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
/linux-4.4.14/arch/sparc/kernel/
H A Dtrampoline_32.S79 /* Start this processor. */
140 /* Start this processor. */
196 /* Start this processor. */
H A Dvmlinux.lds.S61 /* Start of data section */
/linux-4.4.14/drivers/net/ethernet/microchip/
H A Dencx24j600_hw.h33 #define DMACKSUM 0xD8 /* DMA Start Checksum */
34 #define DMACKSUMS 0xDA /* DMA Start Checksum with Seed */
35 #define DMACOPY 0xDC /* DMA Start Copy */
36 #define DMACOPYS 0xDE /* DMA Start Copy and Checksum with Seed */
387 /* Start of the general purpose area in sram */
393 /* Start of the receive buffer */
/linux-4.4.14/drivers/staging/comedi/drivers/addi-data/
H A Dhwdrv_apci3501.c76 * Start / Stop The Selected Timer , Counter or Watchdog
81 * data[1] : 1 Start
/linux-4.4.14/drivers/net/ethernet/micrel/
H A Dks8695net.h49 #define KS8695_DTSC (0x08) /* DMA Transmit Start Command */
50 #define KS8695_DRSC (0x0c) /* DMA Receive Start Command */
/linux-4.4.14/arch/x86/boot/
H A Dcmdline.c38 st_wordstart, /* Start of word/after whitespace */ __cmdline_find_option()
109 st_wordstart, /* Start of word/after whitespace */ __cmdline_find_option_bool()
/linux-4.4.14/net/sctp/
H A Dssnmap.c90 /* Start 'in' stream just after the map header. */ sctp_ssnmap_init()
94 /* Start 'out' stream just after 'in'. */ sctp_ssnmap_init()
/linux-4.4.14/fs/ntfs/
H A Dupcase.c29 static const int uc_run_table[][3] = { /* Start, End, Add */ generate_default_upcase()
46 static const int uc_dup_table[][2] = { /* Start, End */ generate_default_upcase()
/linux-4.4.14/arch/arm/plat-pxa/include/plat/
H A Ddma.h22 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
43 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A DdefBF518.h35 #define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
36 #define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
/linux-4.4.14/net/netlabel/
H A Dnetlabel_user.c82 * netlbl_audit_start_common - Start an audit message
87 * Start an audit message using the type specified in @type and fill the audit
/linux-4.4.14/drivers/s390/char/
H A Dsclp_quiesce.c37 /* Handler for quiesce event. Start shutdown procedure. */ sclp_quiesce_handler()
H A Dsclp_ctl.c53 * Start SCLP request
H A Draw3270.h30 #define TO_SF 0x1d /* Start field */
35 #define TO_SFE 0x29 /* Start field extended */
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Dni_labpc_regs.h38 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */
H A Dicp_multi.c52 #define ICP_MULTI_ADC_CSR_ST BIT(0) /* Start ADC */
61 #define ICP_MULTI_DAC_CSR_ST BIT(0) /* Start DAC */
/linux-4.4.14/drivers/media/platform/s5p-g2d/
H A Dg2d-hw.c110 /* Start G2D engine */ g2d_start()
/linux-4.4.14/arch/tile/kernel/
H A Dvmlinux.lds.S74 _sdata = .; /* Start of data section */
H A Dtime.c111 /* Start up the tile-timer interrupt source on the boot cpu. */ time_init()
176 /* Start out with timer not firing. */ setup_tile_timer()
/linux-4.4.14/arch/x86/lib/
H A Dcmdline.c32 st_wordstart = 0, /* Start of word/after whitespace */ cmdline_find_option_bool()
H A Dmemcpy_32.c100 * Start to prepare for backward copy. memmove()
/linux-4.4.14/arch/xtensa/kernel/
H A Dmxhead.S56 * Start Secondary Processors with NULL pointer to boot params.
/linux-4.4.14/fs/udf/
H A Dudf_i.h13 /* Start logical offset in bytes */
/linux-4.4.14/include/net/irda/
H A Dwrapper.h40 #define STA BOF /* Start flag */
/linux-4.4.14/include/asm-generic/
H A Dsections.h39 /* Start and end of .ctors section - used for constructor calls. */
/linux-4.4.14/include/uapi/linux/
H A Dif_packet.h257 - Start. Frame must be aligned to TPACKET_ALIGNMENT=16
261 - Gap, chosen so that packet data (Start+tp_net) alignes to TPACKET_ALIGNMENT=16
262 - Start+tp_mac: [ Optional MAC header ]
263 - Start+tp_net: Packet data, aligned to TPACKET_ALIGNMENT=16.
H A Domap3isp.h124 * @ver_win_start: Vertical Window Start. Range 0 - 4095.
125 * @hor_win_start: Horizontal Window Start. Range 0 - 4095.
126 * @blk_ver_win_start: Black Vertical Windows Start. Range 0 - 4095.
264 __u16 h_start; /* Horizontal Start Position */
265 __u16 v_start; /* Vertical Start Position */
319 * @fmtsph: Start pixel horizontal from start of the HS sync pulse.
322 * @fmtslv: Start line from start of VS sync pulse for the data reformatter.
347 * @obstpixel: Start Pixel w.r.t. HS pulse in Optical black sample.
H A Dparport.h10 /* Start off with user-visible constants */
H A Dsched.h24 /* 0x02000000 was previously the unused CLONE_STOPPED (Start in stopped state)
/linux-4.4.14/arch/mn10300/kernel/
H A Dvmlinux.lds.S47 _sdata = .; /* Start of rw data section */
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
H A Dams-delta-fiq.h68 #define FIQ_CIRC_BUFF 30 /*Start of circular buffer */
/linux-4.4.14/drivers/watchdog/
H A Dwd501p.h27 #define WDT_SR (io+4) /* Start buzzer on PCI write */
/linux-4.4.14/tools/testing/selftests/powerpc/tm/
H A Dtm-resched-dscr.c11 * Start a transaction, and suspend it (*).
/linux-4.4.14/drivers/acpi/acpica/
H A Devrgnini.c60 * function - Start or stop
122 * function - Start or stop
153 * function - Start or stop
219 /* Start search from the parent object */ acpi_ev_pci_config_region_setup()
396 * function - Start or stop
423 * function - Start or stop
450 * function - Start or stop
H A Dnsparse.c183 ACPI_DEBUG_PRINT((ACPI_DB_PARSE, "**** Start pass 1\n")); acpi_ns_parse_table()
199 ACPI_DEBUG_PRINT((ACPI_DB_PARSE, "**** Start pass 2\n")); acpi_ns_parse_table()
H A Drsio.c200 /* Get the descriptor length (0 or 1 for Start Dpf descriptor) */
230 /* Start with a default descriptor of length 1 */
/linux-4.4.14/drivers/firmware/
H A Dmemmap.c139 * @start: Start of the memory range.
215 * @start: Start of the memory range.
243 * @start: Start of the memory range.
261 * @start: Start of the memory range.
280 * @start: Start of the memory range.
321 * @start: Start of the memory range.
345 * @start: Start of the memory range.
/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h315 #define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
329 #define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
343 #define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
357 #define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
371 #define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
385 #define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
399 #define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
413 #define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
427 #define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
441 #define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
455 #define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
469 #define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
484 #define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
498 #define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
512 #define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
526 #define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
541 #define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
555 #define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
569 #define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
583 #define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
597 #define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
611 #define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
625 #define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
639 #define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
653 #define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
667 #define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
681 #define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
695 #define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
710 #define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
724 #define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
738 #define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
752 #define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
767 #define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
780 #define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
793 #define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
806 #define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
1346 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
/linux-4.4.14/drivers/target/
H A Dtarget_core_fabric_configfs.c68 /* Start of tfc_tpg_mappedlun_cit */
235 /* Start of tfc_tpg_mappedlun_port_cit */
265 /* Start of tfc_tpg_nacl_base_cit */
408 /* Start of tfc_node_fabric_stats_cit */
417 /* Start of tfc_tpg_nacl_cit */
494 /* Start of tfc_tpg_np_base_cit */
514 /* Start of tfc_tpg_np_cit */
560 /* Start of tfc_tpg_port_cit */
763 /* Start of tfc_tpg_port_stat_cit */
788 /* Start of tfc_tpg_lun_cit */
887 /* Start of tfc_tpg_base_cit */
907 /* Start of tfc_tpg_cit */
1000 /* Start of tfc_wwn_fabric_stats_cit */
1009 /* Start of tfc_wwn_cit */
/linux-4.4.14/drivers/staging/rtl8712/
H A Drtl8712_cmd.h92 /* MP_OFFLOAD Start (47~54)*/
205 /* MP_OFFLOAD Start (47~54)*/
/linux-4.4.14/drivers/spi/
H A Dspi-bcm53xx.c108 /* Start SPI transfer */ bcm53xxspi_buf_write()
148 /* Start SPI transfer */ bcm53xxspi_buf_read()
H A Dspi-butterfly.c219 * only bother implementing mode 0. Start it later. butterfly_attach()
267 * Start SPI ... for now, hide that we're two physical busses. butterfly_attach()
/linux-4.4.14/drivers/media/usb/gspca/stv06xx/
H A Dstv06xx_pb0100.h41 #define PB_RSTART 0x01 /* Row Window Start */
42 #define PB_CSTART 0x02 /* Column Window Start */
/linux-4.4.14/drivers/net/fddi/skfp/
H A Dhwt.c48 * Start hardware timer (clock ticks are 16us).
82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */ hwt_start()
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac_dma.h47 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
48 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
/linux-4.4.14/drivers/char/hw_random/
H A Dtx4939-rng.c84 /* Start RNG */ tx4939_rng_data_present()
129 /* Start RNG */ tx4939_rng_probe()
/linux-4.4.14/arch/metag/include/asm/
H A Dl2cache.h97 * Start an initialisation of the L2 cachelines and wait for completion.
109 * Start a writeback of dirty L2 cachelines and wait for completion.
/linux-4.4.14/tools/perf/util/
H A Dprobe-event.h98 int start; /* Start line number */
100 int offset; /* Start line offset */
H A Dprobe-finder.h107 int lno_s; /* Start line number */
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dxdi_msg.h53 Start does set new set of features due to fact that we not know
H A Dpc_init.h60 0 0 -> Wink Start
61 1 0 -> Loop Start
62 0 1 -> Ground Start
/linux-4.4.14/drivers/isdn/sc/
H A Dscioc.h16 #define SCIOCSTART 0x05 /* Start the firmware */
/linux-4.4.14/drivers/media/rc/keymaps/
H A Drc-digitalnow-tinytwin.c38 { 0x000d, KEY_HOMEPAGE }, /* [symbol home] Start */
H A Drc-rc6-mce.c90 { 0x800f046f, KEY_PLAYER }, /* Start media application (NEW) */
/linux-4.4.14/drivers/media/usb/gspca/
H A Dsq905c.c277 PDEBUG(D_STREAM, "Start streaming at high resolution"); sd_start()
283 PDEBUG(D_STREAM, "Start streaming at medium resolution"); sd_start()
289 PERR("Start streaming command failed"); sd_start()
292 /* Start the workqueue function to do the streaming */ sd_start()
H A Djl2005bcd.c460 PDEBUG(D_STREAM, "Start streaming at vga resolution"); sd_start()
464 PDEBUG(D_STREAM, "Start streaming at qvga resolution"); sd_start()
468 PDEBUG(D_STREAM, "Start streaming at cif resolution"); sd_start()
472 PDEBUG(D_STREAM, "Start streaming at qcif resolution"); sd_start()
480 /* Start the workqueue function to do the streaming */ sd_start()
H A Dsq905.c377 PDEBUG(D_STREAM, "Start streaming at high resolution"); sd_start()
381 PDEBUG(D_STREAM, "Start streaming at medium resolution"); sd_start()
385 PDEBUG(D_STREAM, "Start streaming at low resolution"); sd_start()
390 PERR("Start streaming command failed"); sd_start()
393 /* Start the workqueue function to do the streaming */ sd_start()
/linux-4.4.14/drivers/pci/
H A Dof.c73 /* Start looking for a phandle to an MSI controller. */ pci_host_bridge_of_msi_domain()
/linux-4.4.14/drivers/atm/
H A DuPD98401.h109 #define uPD98401_MSH(n) (0x10+(n)) /* Mailbox n Start Address High */
110 #define uPD98401_MSL(n) (0x14+(n)) /* Mailbox n Start Address High */
189 #define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */
190 #define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */
/linux-4.4.14/arch/unicore32/include/mach/
H A Dregs-pm.h65 * PM DDR2 PAD Start Reg PM_DDR2START
/linux-4.4.14/arch/x86/mm/
H A Dtestmmiotrace.c13 MODULE_PARM_DESC(mmio_address, " Start address of the mapping of 16 kB "
/linux-4.4.14/arch/cris/arch-v32/mach-a3/
H A Ddram_init.S32 ; Start clock
/linux-4.4.14/include/sound/
H A Dak4113.h96 /* Block Start & C/U Output Mode */
152 /* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */
211 /* DAT Start ID Counter */
248 /* DAT Start ID Detect, 0 = no detect, 1 = detect */
/linux-4.4.14/include/linux/regulator/
H A Dfixed.h29 * @startup_delay: Start-up time in microseconds
H A Dgpio-regulator.h55 * @startup_delay: Start-up time in microseconds
/linux-4.4.14/arch/score/kernel/
H A Dvmlinux.lds.S52 _sdata = .; /* Start of data section */
/linux-4.4.14/arch/metag/tbx/
H A Dtbistring.c55 /* Start of string table */ __TBIFindStr()
/linux-4.4.14/arch/mn10300/mm/
H A Dcache-smp.c83 * @start: Start address of request
/linux-4.4.14/arch/arm/mach-pxa/
H A Dsaar.c277 SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/
285 SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/
381 SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
389 SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
/linux-4.4.14/drivers/scsi/pm8001/
H A Dpm8001_hwi.h154 * brief the data structure of PHY Start Command
166 * brief the data structure of PHY Start Command
459 * brief the data structure of SAS Diagnostic Start/End Command
460 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
519 * brief the data structure of SATA Start Command
520 * use to describe MPI SATA IO Start Command (64 bytes)
538 * brief the data structure of SSP INI TM Start Command
539 * use to describe MPI SSP INI TM Start Command (64 bytes)
568 * brief the data structure of SSP INI IO Start Command
569 * use to describe MPI SSP INI IO Start Command (64 bytes)
666 * brief the data structure of SAS Diagnostic Start/End Response
667 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
H A Dpm80xx_hwi.h245 * brief the data structure of PHY Start Command
257 * brief the data structure of PHY Start Command
589 * brief the data structure of SAS Diagnostic Start/End Command
590 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
627 * brief the data structure of SATA Start Command
628 * use to describe MPI SATA IO Start Command (64 bytes)
663 * brief the data structure of SSP INI TM Start Command
664 * use to describe MPI SSP INI TM Start Command (64 bytes)
691 * brief the data structure of SSP INI IO Start Command
692 * use to describe MPI SSP INI IO Start Command (64 bytes)
925 * brief the data structure of SAS Diagnostic Start/End Response
926 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
/linux-4.4.14/drivers/media/usb/stk1160/
H A Dstk1160-i2c.c83 /* Start write now */ stk1160_i2c_write_reg()
110 /* Start read now */ stk1160_i2c_read_reg()
145 /* Start read now */ stk1160_i2c_check_for_device()
H A Dstk1160-reg.h70 /* Capture Frame Start Position */
/linux-4.4.14/include/net/sctp/
H A Dcommand.h62 SCTP_CMD_TIMER_START, /* Start a timer. */
63 SCTP_CMD_TIMER_START_ONCE, /* Start a timer once */
74 SCTP_CMD_HB_TIMERS_START, /* Start the heartbeat timers. */
/linux-4.4.14/include/linux/clk/
H A Dat91_pmc.h55 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
57 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
63 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h67 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
143 #define LCSR_SOF (1 << 1) /* Start of frame */
159 #define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */
/linux-4.4.14/sound/pci/emu10k1/
H A Dp17v.h56 #define I2C_A_ADC_START 0x00000100 /*Start I2C transaction */
94 #define P17V_START_AUDIO 0x40 /* Start Audio bit */
96 #define P17V_START_CAPTURE 0x48 /* Start Capture bit */
/linux-4.4.14/firmware/
H A Dihex2fw.c223 case 3: /* Start Segment Address Record */ process_ihex()
224 case 5: /* Start Linear Address Record */ process_ihex()
226 fprintf(stderr, "Bad Start Address record (type %02X) at line %d\n", process_ihex()
/linux-4.4.14/drivers/media/tuners/
H A Dr820t.c149 .freq = 50, /* Start freq, in MHz */
158 .freq = 55, /* Start freq, in MHz */
167 .freq = 60, /* Start freq, in MHz */
176 .freq = 65, /* Start freq, in MHz */
185 .freq = 70, /* Start freq, in MHz */
194 .freq = 75, /* Start freq, in MHz */
203 .freq = 80, /* Start freq, in MHz */
212 .freq = 90, /* Start freq, in MHz */
221 .freq = 100, /* Start freq, in MHz */
230 .freq = 110, /* Start freq, in MHz */
239 .freq = 120, /* Start freq, in MHz */
248 .freq = 140, /* Start freq, in MHz */
257 .freq = 180, /* Start freq, in MHz */
266 .freq = 220, /* Start freq, in MHz */
275 .freq = 250, /* Start freq, in MHz */
284 .freq = 280, /* Start freq, in MHz */
293 .freq = 310, /* Start freq, in MHz */
302 .freq = 450, /* Start freq, in MHz */
311 .freq = 588, /* Start freq, in MHz */
320 .freq = 650, /* Start freq, in MHz */
1119 /* Start Trigger */ r820t_set_tv_standard()
H A Dmt2060_priv.h58 FM1CA : Calibration Start Bit
/linux-4.4.14/init/
H A Dinitramfs.c189 Start, enumerator in enum:state
402 [Start] = do_start,
434 state = Start; flush_buffer()
463 state = Start; unpack_to_rootfs()
469 state = Start; unpack_to_rootfs()
/linux-4.4.14/drivers/mfd/
H A Dtwl4030-power.c48 #define STARTON_SWBUG BIT(7) /* Start on watchdog */
49 #define STARTON_VBUS BIT(5) /* Start on VBUS */
50 #define STARTON_VBAT BIT(4) /* Start on battery insert */
51 #define STARTON_RTC BIT(3) /* Start on RTC */
52 #define STARTON_USB BIT(2) /* Start on USB host */
53 #define STARTON_CHG BIT(1) /* Start on charger */
54 #define STARTON_PWON BIT(0) /* Start on PWRON button */
/linux-4.4.14/drivers/target/iscsi/
H A Discsi_target_configfs.c39 /* Start items for lio_target_portal_cit */
196 /* Start items for lio_target_np_cit */
346 /* Start items for lio_target_nacl_attrib_cit */
403 /* Start items for lio_target_nacl_auth_cit */
508 /* Start items for lio_target_nacl_param_cit */
565 /* Start items for lio_target_acl_cit */
814 /* Start items for lio_target_tpg_attrib_cit */
894 /* Start items for lio_target_tpg_auth_cit */
993 /* Start items for lio_target_tpg_param_cit */
1103 /* Start items for lio_target_tpg_cit */
1179 /* Start items for lio_target_tiqn_cit */
1246 /* Start LIO-Target TIQN struct contig_item lio_target_cit */
1332 /* Start lio_target_discovery_auth_cit */
1445 /* Start functions for target_core_fabric_ops */
/linux-4.4.14/drivers/isdn/hisax/
H A Dst5481_b.c127 * Start transferring (flags or data) on the B channel, since
136 // Start transmitting (flags or data) on B channel st5481B_start_xfer()
198 * Start or stop the transfer on the B channel.
/linux-4.4.14/drivers/iio/adc/
H A Dmax1027.c230 /* Start acquisition on conversion register write */ max1027_read_single_value()
338 /* Start acquisition on cnvst */ max1027_set_trigger_state()
352 /* Start acquisition on conversion register write */ max1027_set_trigger_state()
/linux-4.4.14/drivers/media/platform/marvell-ccic/
H A Dmcam-core.h282 #define IRQ_SOF0 0x00000008 /* Start of frame 0 */
283 #define IRQ_SOF1 0x00000010 /* Start of frame 1 */
284 #define IRQ_SOF2 0x00000020 /* Start of frame 2 */
/linux-4.4.14/drivers/media/platform/omap3isp/
H A Disph3a_af.c66 /*Configure Horizontal Start */ h3a_af_setup_regs()
68 /* Configure Vertical Start */ h3a_af_setup_regs()
194 /* Check Horizontal Start */ h3a_af_validate_params()
/linux-4.4.14/include/misc/
H A Dcxl.h112 * Start work on the AFU. This starts an cxl context and associates it with a
155 * // Start context
187 * Start a context associated a struct cxl_ioctl_start_work used by the
/linux-4.4.14/arch/ia64/include/asm/sn/
H A Dshub_mmr.h183 /* Description: Start */
193 /* Description: PTC_1 Start */
215 /* Description: Start */
/linux-4.4.14/tools/testing/selftests/rcutorture/bin/
H A Dkvm.sh312 print "echo ----Start batch: `date`";
313 print "echo ----Start batch: `date` >> " rd "/log";
410 egrep 'Start batch|Starting build\.' $T/script |
/linux-4.4.14/drivers/usb/serial/
H A Dio_edgeport.h129 __u16 Strings[1]; /* Start of string block */
/linux-4.4.14/drivers/staging/sm750fb/
H A Dddk750_swi2c.c41 * Tx Start SDA | | H | | L |
220 /* Start I2C */ sw_i2c_start()
459 /* Send the Start signal */ sm750_sw_i2c_read_reg()
500 /* Send the Start signal */ sm750_sw_i2c_write_reg()
H A Dddk750_hwi2c.c123 /* Start the I2C */ hw_i2c_write_data()
186 /* Start the I2C */ hw_i2c_read_data()
/linux-4.4.14/drivers/s390/cio/
H A Ddevice_fsm.c429 * Start device recognition.
590 /* Start initial path verification. */ ccw_device_online()
649 /* Start Set Path Group commands. */ ccw_device_offline()
811 /* Start delayed path verification. */ ccw_device_irq()
888 /* Start delayed path verification. */ ccw_device_w4sense()
896 /* Start delayed path verification. */ ccw_device_killing_irq()
914 /* Start delayed path verification. */ ccw_device_killing_timeout()
932 /* Start delayed path verification. */ ccw_device_kill_io()
942 /* Start verification after current task finished. */ ccw_device_delay_verify()
H A Ddevice_ops.c173 * Start a S/390 channel program. When the interrupt arrives, the
249 * Start a S/390 channel program. When the interrupt arrives, the
291 * Start a S/390 channel program. When the interrupt arrives, the
322 * Start a S/390 channel program. When the interrupt arrives, the
498 * Start the tcw on the given ccw device. Return zero on success, non-zero
544 * Start the tcw on the given ccw device. Return zero on success, non-zero
568 * Start the tcw on the given ccw device. Return zero on success, non-zero
587 * Start the tcw on the given ccw device. Return zero on success, non-zero
/linux-4.4.14/drivers/scsi/
H A Daha1542.h38 #define CMD_START_SCSI 0x02 /* Start SCSI Command */
/linux-4.4.14/drivers/staging/fsl-mc/include/
H A Dmc-private.h45 * @start_mc_offset: Start MC offset of the range being translated
/linux-4.4.14/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c52 /* Start Ver and Hor Sync Generator */ StartVTG()
/linux-4.4.14/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c68 * Start hdmi phy macro cell tx3g4c28
/linux-4.4.14/drivers/media/platform/exynos4-is/
H A Dfimc-lite-reg.h89 /* Camera Output DMA Start Address */
/linux-4.4.14/drivers/input/keyboard/
H A Dipaq-micro-keys.c37 KEY_HOMEPAGE, /* 5: Start (looks like swoopy arrow) */
/linux-4.4.14/drivers/media/usb/pvrusb2/
H A Dpvrusb2-io.h89 /* Start reading into given buffer (kill it if needed) */
/linux-4.4.14/drivers/net/wireless/rt2x00/
H A Drt2x00lib.h215 * rt2x00link_start_tuner - Start periodic link tuner work
255 * rt2x00link_start_watchdog - Start periodic watchdog monitoring
274 * rt2x00link_start_agc - Start periodic gain calibration
280 * rt2x00link_start_vcocal - Start periodic VCO calibration
/linux-4.4.14/drivers/nfc/s3fwrn5/
H A Dnci.c120 /* Start rfreg configuration */ s3fwrn5_nci_rf_configure()
/linux-4.4.14/arch/xtensa/include/asm/
H A Dmmu_context.h73 * Start new asid cycle; continue counting with next get_new_mmu_context()
H A Dvectors.h53 /* Image Virtual Start Address */
/linux-4.4.14/arch/cris/arch-v32/mach-fs/
H A Ddram_init.S96 ; Start refresh
/linux-4.4.14/arch/powerpc/include/asm/
H A Dmpc5121.h68 u32 start_addr; /* SCLPC Start Address Register */
/linux-4.4.14/arch/mips/kernel/
H A Dvmlinux.lds.S84 _sdata = .; /* Start of data section */
/linux-4.4.14/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c78 * Start scaling from the high end down until we find something shoc_clk_init()
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
H A Dsmp-shx3.c101 /* Start up secondary processor by sending a reset */ shx3_start_cpu()
/linux-4.4.14/arch/mips/oprofile/
H A Dop_model_loongson2.c94 /* Start all counters on current CPU */ loongson2_cpu_start()
/linux-4.4.14/arch/mips/sgi-ip22/
H A Dip22-time.c37 /* Start the counter. */ dosample()
/linux-4.4.14/arch/parisc/kernel/
H A Dvmlinux.lds.S88 /* Start of data section */
/linux-4.4.14/arch/hexagon/include/asm/
H A Dmem-layout.h71 * Start of vmalloc virtual address space for kernel;
/linux-4.4.14/arch/m68k/68360/
H A Dconfig.c104 /* Start timer 1: */ hw_timer_init()
/linux-4.4.14/arch/arm/mach-omap2/
H A Domap_phy_internal.c93 * Start the on-chip PHY and its PLL. am35x_musb_phy_power()
/linux-4.4.14/arch/arm/include/asm/hardware/
H A Dsa1111.h155 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
157 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
160 * SADRSA Serial Audio DMA Receive Buffer Start Address A
162 * SADRSB Serial Audio DMA Receive Buffer Start Address B
/linux-4.4.14/tools/build/
H A Dfixdep.c104 * Start searching for next token immediately after the first parse_dep_file()
/linux-4.4.14/tools/testing/selftests/timers/
H A Dalarmtimer-suspend.c162 printf("Start time (%s): %ld:%ld\n", clockstring(alarm_clock_id), main()
/linux-4.4.14/tools/testing/selftests/x86/
H A Dsysret_ss_attrs.c59 * Start a busy-looping thread on the same CPU we're on. main()
/linux-4.4.14/drivers/usb/host/whci/
H A Dhcd.c38 * Start the wireless host controller.
40 * Start device notification.
/linux-4.4.14/drivers/rtc/
H A Drtc-pcf2123.c206 /* Start the counter */ pcf2123_rtc_set_time()
277 /* Start the counter */ pcf2123_probe()
H A Drtc-tps80031.c121 dev_err(dev->parent, "Start RTC failed, err = %d\n", ret); tps80031_rtc_set_time()
249 /* Start RTC */ tps80031_rtc_probe()
/linux-4.4.14/drivers/misc/vmw_vmci/
H A Dvmci_queue_pair.h43 u64 ppn_va; /* Start VA of queue pair PPNs. */
52 u64 va; /* Start VA of queue pair PPNs. */
/linux-4.4.14/drivers/media/pci/cobalt/
H A Dcobalt-i2c.c134 /* Write + Start */ cobalt_tx_bytes()
189 /* Read + Start */ cobalt_rx_bytes()
/linux-4.4.14/drivers/misc/eeprom/
H A Deeprom_93cx6.c108 * Start writing all bits. eeprom_93cx6_write_bits()
148 * Start reading all bits. eeprom_93cx6_read_bits()
/linux-4.4.14/drivers/net/ethernet/tundra/
H A Dtsi108_eth.h299 #define TSI108_TX_SOF (1 << 1) /* Start of frame; first frag. of packet */
327 #define TSI108_RX_SOF (1 << 1) /* Start of frame; first frag. of packet */
/linux-4.4.14/drivers/net/wan/
H A Dhd64570.h191 #define CMD_TX_ENABLE 0x02 /* Start transmitter */
192 #define CMD_RX_ENABLE 0x12 /* Start receiver */
/linux-4.4.14/drivers/net/ethernet/qlogic/qed/
H A Dqed_sp.h329 * @brief qed_sp_pf_start - PF Function Start Ramrod
337 * to the internal RAM of the UStorm by the Function Start Ramrod.
/linux-4.4.14/drivers/net/ethernet/i825xx/
H A Dether1.h195 #define SCB_CMDRXSTART (1 << 4) /* Start (at rfa_offset) */
199 #define SCB_CMDCUCSTART (1 << 8) /* Start (at cbl_offset) */
/linux-4.4.14/drivers/cpuidle/
H A Dcpuidle-big_little.c198 /* Start at index 1, index 0 standard WFI */ bl_idle_init()
203 /* Start at index 1, index 0 standard WFI */ bl_idle_init()
/linux-4.4.14/arch/x86/platform/ts5500/
H A Dts5500.c64 #define TS5500_ADC_CONV_INIT_LSB_ADDR 0x196 /* Start conv. / LSB register */
258 /* Start conversion (ensure the 3 MSB are set to 0) */ ts5500_adc_convert()
/linux-4.4.14/fs/nilfs2/
H A Dsegment.h122 * @sc_wait_task: Start/end wait queue to control segctord task
129 * @sc_lseg_stime: Start time of the latest logical segment
/linux-4.4.14/include/drm/
H A Ddrm_vma_manager.h73 * @start: Start address (page-based, not byte-based)
153 * Start address of @node for page-based addressing. 0 if the node does not
/linux-4.4.14/arch/powerpc/sysdev/
H A Di8259.c239 outb(0x11, 0x20); /* Start init sequence */ i8259_init()
245 outb(0x11, 0xA0); /* Start init sequence */ i8259_init()

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