Searched refs:SOR_PWM_CTL_CLK_SEL (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/tegra/
H A Dsor.h187 #define SOR_PWM_CTL_CLK_SEL (1 << 30) macro
H A Dsor.c401 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ tegra_sor_setup_pwm()

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