Searched refs:SOR_LANE_SEQ_CTL (Results 1 - 2 of 2) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/tegra/ |
| H A D | sor.c | 748 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); tegra_sor_power_down()
753 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); tegra_sor_power_down()
894 DUMP_REG(SOR_LANE_SEQ_CTL); tegra_sor_show_regs()
1368 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); tegra_sor_edp_enable()
1371 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); tegra_sor_edp_enable()
1845 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); tegra_sor_hdmi_enable()
1854 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); tegra_sor_hdmi_enable()
1857 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); tegra_sor_hdmi_enable()
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| H A D | sor.h | 147 #define SOR_LANE_SEQ_CTL 0x21 macro
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