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Searched refs:SM (Results 1 – 40 of 40) sorted by relevance

/linux-4.4.14/drivers/net/wireless/ath/ath9k/
Dar9003_aic.c181 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
182 SM(127, AR_PHY_AIC_CAL_MAX_HOP_COUNT) | in ar9003_aic_cal_start()
183 SM(min_valid_count, AR_PHY_AIC_CAL_MIN_VALID_COUNT) | in ar9003_aic_cal_start()
184 SM(37, AR_PHY_AIC_F_WLAN) | in ar9003_aic_cal_start()
185 SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | in ar9003_aic_cal_start()
186 SM(0, AR_PHY_AIC_CAL_ENABLE) | in ar9003_aic_cal_start()
187 SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | in ar9003_aic_cal_start()
188 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
191 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
192 SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | in ar9003_aic_cal_start()
[all …]
Dar9003_rtt.c77 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); in ar9003_hw_rtt_load_hist_entry()
80 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_load_hist_entry()
81 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_load_hist_entry()
82 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_load_hist_entry()
86 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_load_hist_entry()
95 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); in ar9003_hw_rtt_load_hist_entry()
146 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_fill_hist_entry()
147 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_fill_hist_entry()
148 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_fill_hist_entry()
153 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_fill_hist_entry()
Dbtcoex.c76 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) | in ath9k_hw_init_btcoex_hw()
77 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | in ath9k_hw_init_btcoex_hw()
78 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | in ath9k_hw_init_btcoex_hw()
79 SM(ath_bt_config.bt_mode, AR_BT_MODE) | in ath9k_hw_init_btcoex_hw()
80 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) | in ath9k_hw_init_btcoex_hw()
81 SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) | in ath9k_hw_init_btcoex_hw()
82 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) | in ath9k_hw_init_btcoex_hw()
83 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) | in ath9k_hw_init_btcoex_hw()
84 SM(qnum, AR_BT_QCU_THRESH); in ath9k_hw_init_btcoex_hw()
87 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | in ath9k_hw_init_btcoex_hw()
[all …]
Dar9003_mci.c855 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
856 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
857 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
858 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
859 SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
860 SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
861 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
862 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
863 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
874 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | in ar9003_mci_set_btcoex_ctrl_9565_2ANT()
[all …]
Dar9002_phy.c238 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9002_hw_spur_mitigate()
267 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar9002_hw_spur_mitigate()
268 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar9002_hw_spur_mitigate()
319 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
320 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
323 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
325 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
461 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); in ar9002_hw_set_bt_ant_diversity()
462 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9002_hw_set_bt_ant_diversity()
463 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9002_hw_set_bt_ant_diversity()
[all …]
Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); in ath9k_hw_updatetxtriglevel()
391 SM(cwMin, AR_D_LCL_IFS_CWMIN) | in ath9k_hw_resettxqueue()
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
396 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ath9k_hw_resettxqueue()
397 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ath9k_hw_resettxqueue()
[all …]
Dar9002_mac.c227 ctl6 = SM(i->keytype, AR_EncrType); in ar9002_set_txdesc()
243 | SM(0, AR_BurstDur); in ar9002_set_txdesc()
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
262 | SM(i->type, AR_FrameType) in ar9002_set_txdesc()
269 ctl6 |= SM(i->aggr_len, AR_AggrLen); in ar9002_set_txdesc()
273 ctl6 |= SM(i->ndelim, AR_PadDelim); in ar9002_set_txdesc()
284 | SM(i->txpower[0], AR_XmitPower0) in ar9002_set_txdesc()
308 | SM(i->rtscts_rate, AR_RTSCTSRate); in ar9002_set_txdesc()
310 ACCESS_ONCE(ads->ds_ctl9) = SM(i->txpower[1], AR_XmitPower1); in ar9002_set_txdesc()
311 ACCESS_ONCE(ads->ds_ctl10) = SM(i->txpower[2], AR_XmitPower2); in ar9002_set_txdesc()
[all …]
Deeprom_9287.c499 regval = SM(pdGainOverlap_t2, in ath9k_hw_set_ar9287_power_cal_table()
501 | SM(gainBoundaries[0], in ath9k_hw_set_ar9287_power_cal_table()
503 | SM(gainBoundaries[1], in ath9k_hw_set_ar9287_power_cal_table()
505 | SM(gainBoundaries[2], in ath9k_hw_set_ar9287_power_cal_table()
507 | SM(gainBoundaries[3], in ath9k_hw_set_ar9287_power_cal_table()
930 SM(pModal->iqCalICh[i], in ath9k_hw_ar9287_set_board_values()
932 SM(pModal->iqCalQCh[i], in ath9k_hw_ar9287_set_board_values()
963 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_ar9287_set_board_values()
964 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) in ath9k_hw_ar9287_set_board_values()
965 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) in ath9k_hw_ar9287_set_board_values()
[all …]
Dar5008_phy.c461 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar5008_hw_spur_mitigate()
471 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar5008_hw_spur_mitigate()
472 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar5008_hw_spur_mitigate()
903 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
906 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
908 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
911 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
913 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
926 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
928 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
Dar9003_mac.c74 | SM(0, AR_BurstDur); in ar9003_set_txdesc()
90 ctl17 = SM(i->keytype, AR_EncrType); in ar9003_set_txdesc()
104 | SM(i->txpower[0], AR_XmitPower0) in ar9003_set_txdesc()
113 SM(i->keyix, AR_DestIdx) : 0) in ar9003_set_txdesc()
114 | SM(i->type, AR_FrameType) in ar9003_set_txdesc()
122 ctl17 |= SM(i->aggr_len, AR_AggrLen); in ar9003_set_txdesc()
126 ctl17 |= SM(i->ndelim, AR_PadDelim); in ar9003_set_txdesc()
136 ctl12 |= SM(val, AR_PAPRDChainMask); in ar9003_set_txdesc()
151 | SM(i->rtscts_rate, AR_RTSCTSRate); in ar9003_set_txdesc()
155 ACCESS_ONCE(ads->ctl20) = SM(i->txpower[1], AR_XmitPower1); in ar9003_set_txdesc()
[all …]
Deeprom_4k.c417 SM(pdGainOverlap_t2, in ath9k_hw_set_4k_power_cal_table()
419 | SM(gainBoundaries[0], in ath9k_hw_set_4k_power_cal_table()
421 | SM(gainBoundaries[1], in ath9k_hw_set_4k_power_cal_table()
423 | SM(gainBoundaries[2], in ath9k_hw_set_4k_power_cal_table()
425 | SM(gainBoundaries[3], in ath9k_hw_set_4k_power_cal_table()
780 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | in ath9k_hw_4k_set_gain()
781 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF), in ath9k_hw_4k_set_gain()
857 regVal |= SM(ant_div_control1, in ath9k_hw_4k_set_board_values()
859 regVal |= SM(ant_div_control2, in ath9k_hw_4k_set_board_values()
861 regVal |= SM((ant_div_control2 >> 2), in ath9k_hw_4k_set_board_values()
[all …]
Dar9003_phy.c607 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); in ar9003_hw_compute_pll_control_soc()
610 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
612 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
614 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); in ar9003_hw_compute_pll_control_soc()
624 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
627 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
629 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
631 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); in ar9003_hw_compute_pll_control()
1477 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1478 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
[all …]
Deeprom_def.c488 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN), in ath9k_hw_def_set_gain()
491 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN), in ath9k_hw_def_set_gain()
505 SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN), in ath9k_hw_def_set_gain()
508 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN), in ath9k_hw_def_set_gain()
545 SM(pModal->iqCalICh[i], in ath9k_hw_def_set_board_values()
547 SM(pModal->iqCalQCh[i], in ath9k_hw_def_set_board_values()
614 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_def_set_board_values()
615 | SM(pModal->txEndToXpaOff, in ath9k_hw_def_set_board_values()
617 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
619 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
[all …]
Dmac.h21 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
24 (SM((_series)[_index].Rate, AR_XmitRate##_index))
27 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
38 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
Dhw.c711 SM(2, AR_QOS_NO_ACK_TWO_BIT) | in ath9k_hw_init_qos()
712 SM(5, AR_QOS_NO_ACK_BIT_OFF) | in ath9k_hw_init_qos()
713 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); in ath9k_hw_init_qos()
1118 SM(rx_lat, AR_USEC_RX_LAT) | in ath9k_hw_init_global_settings()
1119 SM(tx_lat, AR_USEC_TX_LAT), in ath9k_hw_init_global_settings()
2313 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) in ath9k_hw_set_sta_beacon_timers()
2322 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); in ath9k_hw_set_sta_beacon_timers()
3069 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3072 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3104 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | in ath9k_hw_gen_timer_stop()
[all …]
Dar9003_eeprom.c4393 val = SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) | in ar9003_hw_selfgen_tpc_txpower()
4394 SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) | in ar9003_hw_selfgen_tpc_txpower()
4395 SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT); in ar9003_hw_selfgen_tpc_txpower()
4397 val = SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) | in ar9003_hw_selfgen_tpc_txpower()
4398 SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) | in ar9003_hw_selfgen_tpc_txpower()
4399 SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT); in ar9003_hw_selfgen_tpc_txpower()
Dhw.h121 #define SM(_v, _f) (((_v) << _f##_S) & _f) macro
/linux-4.4.14/drivers/net/wireless/ath/ath6kl/
Dhif.c216 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
219 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
580 SM(INT_STATUS_ENABLE_ERROR, 0x01) | in ath6kl_hif_enable_intrs()
581 SM(INT_STATUS_ENABLE_CPU, 0x01) | in ath6kl_hif_enable_intrs()
582 SM(INT_STATUS_ENABLE_COUNTER, 0x01); in ath6kl_hif_enable_intrs()
588 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
595 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | in ath6kl_hif_enable_intrs()
596 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); in ath6kl_hif_enable_intrs()
602 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
Dtarget.h133 #define SM(f, v) (((v) << f##_S) & f) macro
Dinit.c1448 param |= SM(SYSTEM_SLEEP_DISABLE, 1); in ath6kl_init_upload()
1466 param = SM(CPU_CLOCK_STANDARD, 1); in ath6kl_init_upload()
1476 param = SM(LPO_CAL_ENABLE, 1); in ath6kl_init_upload()
/linux-4.4.14/Documentation/devicetree/bindings/display/
Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/linux-4.4.14/arch/m68k/fpsp040/
Ddecbin.S31 | adds and muls in FP0. Set the sign according to SM.
40 | added if SM = 1 and subtracted if SM = 0. Scale the
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE}
Dbindec.S903 bges mant_p |if pos, don't set SM
904 moveql #2,%d0 |move 2 in to d0 for SM
/linux-4.4.14/Documentation/filesystems/nfs/
Dnfs-rdma.txt175 If you are using InfiniBand, make sure there is a Subnet Manager (SM)
176 running on the network. If your IB switch has an embedded SM, you can
177 use it. Otherwise, you will need to run an SM, such as OpenSM, on one
180 If an SM is running on your network, you should see the following:
/linux-4.4.14/drivers/net/wireless/ath/ath10k/
Dhtt_tx.c622 flags0 |= SM(skb_cb->txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx()
625 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx()
662 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); in ath10k_htt_tx()
663 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); in ath10k_htt_tx()
Dcore.h42 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) macro
Dhtc.c647 flags |= SM(tx_alloc, ATH10K_HTC_CONN_FLAGS_RECV_ALLOC); in ath10k_htc_connect_service()
Dce.c298 desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA); in ath10k_ce_send_nolock()
Dmac.c1139 rts_cts |= SM(WMI_RTSCTS_ENABLED, WMI_RTSCTS_SET); in ath10k_recalc_rtscts_prot()
1142 rts_cts |= SM(WMI_RTSCTS_ACROSS_SW_RETRIES, in ath10k_recalc_rtscts_prot()
1145 rts_cts |= SM(WMI_RTSCTS_FOR_SECOND_RATESERIES, in ath10k_recalc_rtscts_prot()
4250 value |= SM(nsts, WMI_TXBF_STS_CAP_OFFSET); in ath10k_mac_set_txbf_conf()
4255 value |= SM(sound_dim, WMI_BF_SOUND_DIM_OFFSET); in ath10k_mac_set_txbf_conf()
Dwmi.c1639 cmd |= SM(cmd_id, WMI_CMD_HDR_CMD_ID); in ath10k_wmi_cmd_send_nowait()
6324 info0 = SM(max_mcs, WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX) | in ath10k_wmi_peer_assoc_fill_10_2()
6325 SM(max_nss, WMI_PEER_ASSOC_INFO0_MAX_NSS); in ath10k_wmi_peer_assoc_fill_10_2()
6553 cfg = SM(log_level, in ath10k_wmi_op_gen_dbglog_cfg()
6557 cfg = SM(ATH10K_DBGLOG_LEVEL_WARN, in ath10k_wmi_op_gen_dbglog_cfg()
Dhtt_rx.c1911 tid = SM(resp->rx_in_ord_ind.info, HTT_RX_IN_ORD_IND_INFO_TID); in ath10k_htt_rx_in_ord_ind()
Dwmi-tlv.c2763 peer_qos |= SM(sp, WMI_TLV_TDLS_PEER_SP); in ath10k_wmi_tlv_prepare_peer_qos()
/linux-4.4.14/net/ipv4/
DKconfig241 bool "IP: PIM-SM version 1 support"
250 Say Y if you want to use PIM-SM v1. Note that you can say N here if
254 bool "IP: PIM-SM version 2 support"
/linux-4.4.14/drivers/usb/storage/
DKconfig194 Note that this driver does not support SM cards.
/linux-4.4.14/arch/arm/boot/dts/
Dste-snowball.dts431 * Mux in "SM" which is used for the
/linux-4.4.14/net/ipv6/
DKconfig273 bool "IPv6: PIM-SM version 2 support"
/linux-4.4.14/Documentation/sound/oss/
DREADME.OSS492 SM Wave and AudioTrix Pro) support the OPL4 mode using MPU401
764 SM Games). If your card was in the list of supported cards (above),
925 NOTE! Don't enable the SM Games option (asked by the configuration program)
927 (not a SM Wave or SM16).
937 I know just Thunderboard and SM Games. Other cards require some kind of
1230 The Logitech SoundMan Wave (don't confuse this with the SM16 or SM Games) is
1234 you have a SM Wave immediately after asking the second DMA channel of jazz16.
1246 NOTE! Don't answer 'y' when the driver asks about SM Games support
/linux-4.4.14/Documentation/networking/
Dlapb-module.txt83 1 [SM]LP operation (0=LAPB_SLP 1=LAPB=MLP).
/linux-4.4.14/Documentation/DocBook/media/
Dfieldseq_bt.gif.b64288 HzWHT/GBswdKWzjmOrVww7GIYy6GHzdRdziL12xSV/NSn3jikvh0/7SM/22KY7dItziLv3hzQ49O
/linux-4.4.14/sound/oss/
DKconfig418 SM Games). For an unknown card you may answer Y if the card claims