Searched refs:SIMD (Results 1 – 7 of 7) sorted by relevance
87 uint32_t SIMD:2; /* SIMD id */ member
535 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; in dbgdev_wave_control_set_registers()
17 * $#-way unrolled TILE-Gx SIMD for RAID-6 math.
496 in IETF protocols. This is the x86_64 assembler implementation using SIMD670 using powerpc SPE SIMD instruction set.681 multiple data lanes concurrently with SIMD instructions for707 implemented using powerpc SPE SIMD instruction set.1254 This is the x86_64 assembler implementation using SIMD instructions.
2348 bool "Support for the MIPS SIMD Architecture"2352 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers2353 and a set of SIMD instructions to operate on them. When this option
2113 bool "Advanced SIMD (NEON) Extension support"2116 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2059 arm64 core/FP-SIMD registers have the following id bit patterns. Note2090 if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector3548 This capability allows the use of the MIPS SIMD Architecture (MSA) by the guest.